1/* 2 * (C) Copyright 2009-2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * icon.h - configuration for Mosaixtech ICON (440SPe) 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 */ 34#define CONFIG_ICON 1 /* Board is icon */ 35#define CONFIG_4xx 1 /* ... PPC4xx family */ 36#define CONFIG_440 1 /* ... PPC440 family */ 37#define CONFIG_440SPE 1 /* Specifc SPe support */ 38 39#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 40 41#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ 42#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ 43 44/* 45 * Include common defines/options for all AMCC eval boards 46 */ 47#define CONFIG_HOSTNAME icon 48#include "amcc-common.h" 49 50#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 51#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ 52 53/* 54 * Base addresses -- Note these are effective addresses where the 55 * actual resources get mapped (not physical addresses) 56 */ 57#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ 58#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ 59 60#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ 61#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ 62#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE 63 64#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ 65#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ 66#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ 67 68#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 69#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 70#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 71#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 72#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 73#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 74 75/* base address of inbound PCIe window */ 76#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL 77 78/* System RAM mapped to PCI space */ 79#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE 80#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE 81#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) 82 83#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ 84#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 85#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 86 87#define CONFIG_SYS_FLASH_SIZE (64 << 20) 88#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ 89#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 90#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 91#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ 92 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) 93 94/* 95 * Initial RAM & stack pointer (placed in internal SRAM) 96 */ 97#define CONFIG_SYS_TEMP_STACK_OCM 1 98#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE 99#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ 100#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */ 101 102#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 103 GENERATED_GBL_DATA_SIZE) 104#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) 105 106/* 107 * Serial Port 108 */ 109#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 110#undef CONFIG_SYS_EXT_SERIAL_CLOCK 111 112/* 113 * DDR2 SDRAM 114 */ 115#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ 116#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ 117#define CONFIG_DDR_ECC /* with ECC support */ 118#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ 119 120/* 121 * I2C 122 */ 123#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 124 125#define CONFIG_I2C_MULTI_BUS 126#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ 127 128#define CONFIG_SYS_I2C_MULTI_EEPROMS 129#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 130#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 131#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 132#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 133 134/* I2C bootstrap EEPROM */ 135#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 136#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 137#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 138 139/* I2C RTC */ 140#define CONFIG_RTC_M41T11 141#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 142#define CONFIG_SYS_I2C_RTC_ADDR 0x68 143#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ 144 145/* 146 * Video options 147 */ 148#define CONFIG_VIDEO 149 150#ifdef CONFIG_VIDEO 151#define CONFIG_VIDEO_SM501 152#define CONFIG_VIDEO_SM501_32BPP 153#define CONFIG_VIDEO_SM501_PCI 154#define VIDEO_FB_LITTLE_ENDIAN 155#define CONFIG_CFB_CONSOLE 156#define CONFIG_VIDEO_LOGO 157#define CONFIG_CONSOLE_EXTRA_INFO 158#define CONFIG_VGA_AS_SINGLE_DEVICE 159#define CONFIG_VIDEO_SW_CURSOR 160#define CONFIG_VIDEO_BMP_RLE8 161#define CONFIG_SPLASH_SCREEN 162#define CFG_CONSOLE_IS_IN_ENV 163#endif 164 165/* 166 * Environment 167 */ 168#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ 169 170/* 171 * Default environment variables 172 */ 173#define CONFIG_EXTRA_ENV_SETTINGS \ 174 CONFIG_AMCC_DEF_ENV \ 175 CONFIG_AMCC_DEF_ENV_POWERPC \ 176 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 177 "kernel_addr=fc000000\0" \ 178 "fdt_addr=fc1e0000\0" \ 179 "ramdisk_addr=fc200000\0" \ 180 "pciconfighost=1\0" \ 181 "pcie_mode=RP:RP:RP\0" \ 182 "" 183 184/* 185 * Commands additional to the ones defined in amcc-common.h 186 */ 187#define CONFIG_CMD_CHIP_CONFIG 188#define CONFIG_CMD_DATE 189#define CONFIG_CMD_EXT2 190#define CONFIG_CMD_FAT 191#define CONFIG_CMD_PCI 192#define CONFIG_CMD_SDRAM 193#define CONFIG_CMD_SNTP 194#ifdef CONFIG_VIDEO 195#define CONFIG_CMD_BMP 196#endif 197 198#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ 199#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ 200#define CONFIG_HAS_ETH0 201#define CONFIG_PHY_RESET /* reset phy upon startup */ 202#define CONFIG_PHY_RESET_DELAY 1000 203#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ 204#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ 205 206/* 207 * FLASH related 208 */ 209#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 210#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 211#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ 212#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ 213 214#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ 216#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ 217 218#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 219#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 220 221#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 222#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ 223 224#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 225#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 226#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ 227 228/* Address and size of Redundant Environment Sector */ 229#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) 230#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 231 232/* 233 * PCI stuff 234 */ 235/* General PCI */ 236#define CONFIG_PCI /* include pci support */ 237#define CONFIG_PCI_PNP /* do pci plug-and-play */ 238#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 239#define CONFIG_PCI_CONFIG_HOST_BRIDGE 240#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ 241 242/* Board-specific PCI */ 243#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ 244#undef CONFIG_SYS_PCI_MASTER_INIT 245 246#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ 247#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 248 249/* 250 * Xilinx System ACE support 251 */ 252#define CONFIG_SYSTEMACE /* Enable SystemACE support */ 253#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ 254#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE 255#define CONFIG_DOS_PARTITION 256 257/* 258 * External Bus Controller (EBC) Setup 259 */ 260 261/* Memory Bank 0 (Flash) initialization */ 262#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ 263 EBC_BXAP_TWT_ENCODE(7) | \ 264 EBC_BXAP_BCE_DISABLE | \ 265 EBC_BXAP_BCT_2TRANS | \ 266 EBC_BXAP_CSN_ENCODE(0) | \ 267 EBC_BXAP_OEN_ENCODE(0) | \ 268 EBC_BXAP_WBN_ENCODE(0) | \ 269 EBC_BXAP_WBF_ENCODE(0) | \ 270 EBC_BXAP_TH_ENCODE(0) | \ 271 EBC_BXAP_RE_DISABLED | \ 272 EBC_BXAP_SOR_DELAYED | \ 273 EBC_BXAP_BEM_WRITEONLY | \ 274 EBC_BXAP_PEN_DISABLED) 275#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ 276 EBC_BXCR_BS_64MB | \ 277 EBC_BXCR_BU_RW | \ 278 EBC_BXCR_BW_16BIT) 279 280/* Memory Bank 1 (Xilinx System ACE controller) initialization */ 281#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ 282 EBC_BXAP_TWT_ENCODE(4) | \ 283 EBC_BXAP_BCE_DISABLE | \ 284 EBC_BXAP_BCT_2TRANS | \ 285 EBC_BXAP_CSN_ENCODE(0) | \ 286 EBC_BXAP_OEN_ENCODE(0) | \ 287 EBC_BXAP_WBN_ENCODE(0) | \ 288 EBC_BXAP_WBF_ENCODE(0) | \ 289 EBC_BXAP_TH_ENCODE(0) | \ 290 EBC_BXAP_RE_DISABLED | \ 291 EBC_BXAP_SOR_NONDELAYED | \ 292 EBC_BXAP_BEM_WRITEONLY | \ 293 EBC_BXAP_PEN_DISABLED) 294#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ 295 EBC_BXCR_BS_1MB | \ 296 EBC_BXCR_BU_RW | \ 297 EBC_BXCR_BW_16BIT) 298 299/* 300 * Initialize EBC CONFIG - 301 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC 302 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 303 */ 304#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ 305 EBC_CFG_PTD_ENABLE | \ 306 EBC_CFG_RTC_16PERCLK | \ 307 EBC_CFG_ATC_PREVIOUS | \ 308 EBC_CFG_DTC_PREVIOUS | \ 309 EBC_CFG_CTC_PREVIOUS | \ 310 EBC_CFG_OEO_PREVIOUS | \ 311 EBC_CFG_EMC_DEFAULT | \ 312 EBC_CFG_PME_DISABLE | \ 313 EBC_CFG_PR_16) 314 315/* 316 * GPIO Setup 317 */ 318#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 319#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 320#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 321#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 322 323#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ 324 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ 325 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ 326 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) 327#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) 328#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) 329#define CONFIG_SYS_GPIO_ODR 0 330 331#endif /* __CONFIG_H */ 332