LXR uboot/include/configs/km8xx.h

   1/*
   2 * (C) Copyright 2009
   3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * configuration options, keymile 8xx board specific
  26 */
  27
  28#ifndef __CONFIG_KM8XX_H
  29#define __CONFIG_KM8XX_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_KM8XX            1       /* on a km8xx board */
  37
  38/* include common defines/options for all Keymile boards */
  39#include "keymile-common.h"
  40
  41#if defined(CONFIG_KMSUPX4)
  42#undef  CONFIG_I2C_MUX                  /* no I2C mux on this board */
  43#endif
  44
  45#define CONFIG_8xx_GCLK_FREQ            66000000
  46
  47#define CONFIG_SYS_SMC_UCODE_PATCH      1       /* Relocate SMC1 */
  48#define CONFIG_SYS_SMC_DPMEM_OFFSET     0x1fc0
  49#define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1 */
  50#define CONFIG_SYS_SMC_RXBUFLEN 128
  51#define CONFIG_SYS_MAXIDLE      10
  52
  53#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR   0x1eb0  /* In case of SMC relocation,
  54                                                 * the default value is not
  55                                                 * working
  56                                                 */
  57
  58#define BOOTFLASH_START F0000000
  59#define CONFIG_PRAM     512     /* protected RAM [KBytes] */
  60
  61#define CONFIG_PREBOOT  "echo;" \
  62        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  63        "echo"
  64
  65#define BOOTFLASH_START F0000000
  66#define CONFIG_PRAM     512     /* protected RAM [KBytes] */
  67
  68#if defined(CONFIG_MGSUVD)
  69#define CONFIG_ENV_IVM  "EEprom_ivm=pca9544a:70:4 \0"
  70#else
  71#define CONFIG_ENV_IVM  ""
  72#endif
  73
  74#define MTDIDS_DEFAULT          "nor0=app"
  75#define MTDPARTS_DEFAULT \
  76        "mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free),"  \
  77        "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
  78        "768k(cfg)"
  79
  80#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  81        CONFIG_KM_DEF_ENV                                               \
  82        "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  83        "addcon=setenv bootargs ${bootargs} "                           \
  84                "console=ttyCPM0,${baudrate}\0"                         \
  85        "mtdids=nor0=app \0"                                            \
  86        "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
  87        "partition=nor0,9 \0"                                           \
  88        "new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0"  \
  89        CONFIG_ENV_IVM                                                  \
  90        ""
  91
  92#undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
  93
  94#define CONFIG_TIMESTAMP                /* but print image timestmps    */
  95
  96/*
  97 * Low Level Configuration Settings
  98 * (address mappings, register initial values, etc.)
  99 * You should know what you are doing if you make changes here.
 100 */
 101/*-----------------------------------------------------------------------
 102 * Internal Memory Mapped Register
 103 */
 104#define CONFIG_SYS_IMMR         0xFFF00000
 105
 106/*-----------------------------------------------------------------------
 107 * Definitions for initial stack pointer and data area (in DPRAM)
 108 */
 109#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 110#define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 111#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 113
 114/*-----------------------------------------------------------------------
 115 * Start addresses for the final memory configuration
 116 * (Set up by the startup code)
 117 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 118 */
 119#define CONFIG_SYS_SDRAM_BASE           0x00000000
 120#define CONFIG_SYS_FLASH_BASE           0xf0000000
 121#define CONFIG_SYS_MONITOR_LEN          (384 << 10) /* 384 kB for Monitor */
 122#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 123
 124/*
 125 * For booting Linux, the board info and command line data
 126 * have to be in the first 8 MB of memory, since this is
 127 * the maximum mapped by the Linux kernel during initialization.
 128 */
 129#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 130
 131/*-----------------------------------------------------------------------
 132 * FLASH organization
 133 */
 134/* max number of memory banks */
 135#define CONFIG_SYS_MAX_FLASH_BANKS      1
 136#define CONFIG_SYS_FLASH_SIZE           32
 137#define CONFIG_SYS_FLASH_CFI
 138#define CONFIG_FLASH_CFI_DRIVER
 139/* max num of sects on one chip */
 140#define CONFIG_SYS_MAX_FLASH_SECT       256
 141
 142#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* (in ms) */
 143#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* (in ms) */
 144
 145#define CONFIG_ENV_IS_IN_FLASH  1
 146#define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 147#define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment Sector */
 148
 149/* Address and size of Redundant Environment Sector     */
 150#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 151#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 152#define CONFIG_ENV_BUFFER_PRINT         1
 153
 154/*-----------------------------------------------------------------------
 155 * Cache Configuration
 156 */
 157#define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs  */
 158#if defined(CONFIG_CMD_KGDB)
 159#define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value */
 160#endif
 161
 162/*-----------------------------------------------------------------------
 163 * SYPCR - System Protection Control                            11-9
 164 * SYPCR can only be written once after reset!
 165 *-----------------------------------------------------------------------
 166 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 167 */
 168#define CONFIG_SYS_SYPCR        0xffffff89
 169
 170/*-----------------------------------------------------------------------
 171 * SIUMCR - SIU Module Configuration                            11-6
 172 *-----------------------------------------------------------------------
 173 */
 174#if defined(CONFIG_MGSUVD)
 175#define CONFIG_SYS_SIUMCR       0x00610480
 176#else
 177#define CONFIG_SYS_SIUMCR       0x00610400
 178#endif
 179
 180/*-----------------------------------------------------------------------
 181 * TBSCR - Time Base Status and Control                         11-26
 182 *-----------------------------------------------------------------------
 183 * Clear Reference Interrupt Status, Timebase freezing enabled
 184 */
 185#define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 186
 187/*-----------------------------------------------------------------------
 188 * PISCR - Periodic Interrupt Status and Control                11-31
 189 *-----------------------------------------------------------------------
 190 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 191 */
 192#define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 193
 194/*-----------------------------------------------------------------------
 195 * SCCR - System Clock and reset Control Register               15-27
 196 *-----------------------------------------------------------------------
 197 * Set clock output, timebase and RTC source and divider,
 198 * power management and some other internal clocks
 199 */
 200#if defined(CONFIG_MGSUVD)
 201#define SCCR_MASK       0x01800000
 202#else
 203#define SCCR_MASK       0x00000000
 204#endif
 205#define CONFIG_SYS_SCCR 0x01800000
 206
 207#define CONFIG_SYS_DER 0
 208
 209/*
 210 * Init Memory Controller:
 211 *
 212 * BR0/1 and OR0/1 (FLASH)
 213 */
 214
 215#define FLASH_BASE0_PRELIM      0xf0000000      /* FLASH bank #0        */
 216
 217/* used to re-map FLASH both when starting from SRAM or FLASH:
 218 * restrict access enough to keep SRAM working (if any)
 219 * but not too much to meddle with FLASH accesses
 220 */
 221#define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 222#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 223
 224/*
 225 * FLASH timing: Default value of OR0 after reset
 226 */
 227#define CONFIG_SYS_OR0_PRELIM   0xfe000954
 228#define CONFIG_SYS_BR0_PRELIM   0xf0000401
 229
 230/*
 231 * BR1 and OR1 (SDRAM)
 232 *
 233 */
 234#define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 235#define SDRAM_MAX_SIZE          (64 << 20)      /* max 64 MB per bank   */
 236
 237/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
 238#define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 239
 240#define CONFIG_SYS_OR1_PRELIM   0xfc000800
 241#define CONFIG_SYS_BR1_PRELIM   (0x000000C0 | 0x01)
 242
 243#define CONFIG_SYS_MPTPR        0x0200
 244/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
 245   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
 246#if defined(CONFIG_MGSUVD)
 247#define CONFIG_SYS_MBMR 0x10964111
 248#else
 249#define CONFIG_SYS_MBMR 0x20964111
 250#endif
 251#define CONFIG_SYS_MAR          0x00000088
 252
 253/*
 254 * 4096 Rows from SDRAM example configuration
 255 * 1000 factor s -> ms
 256 * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 257 * 4    Number of refresh cycles per period
 258 * 64   Refresh cycle in ms per number of rows
 259 */
 260#define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 261
 262/* GPIO/PIGGY on CS3 initialization values
 263*/
 264#define CONFIG_SYS_PIGGY_BASE   (0x30000000)
 265#if defined(CONFIG_MGSUVD)
 266#define CONFIG_SYS_OR3_PRELIM   (0xfe000d24)
 267#define CONFIG_SYS_BR3_PRELIM   (0x30000401)
 268#else
 269#define CONFIG_SYS_OR3_PRELIM   (0xf8000d26)
 270#define CONFIG_SYS_BR3_PRELIM   (0x30000401)
 271#endif
 272
 273#define CONFIG_SCC3_ENET
 274#define CONFIG_ETHPRIME         "SCC"
 275#define CONFIG_HAS_ETH0
 276
 277/* pass open firmware flat tree */
 278#define CONFIG_OF_LIBFDT        1
 279#define CONFIG_OF_BOARD_SETUP   1
 280
 281#define OF_STDOUT_PATH          "/soc/cpm/serial@a80"
 282
 283/* enable I2C and select the hardware/software driver */
 284#undef  CONFIG_HARD_I2C                 /* I2C with hardware support */
 285#define CONFIG_SOFT_I2C         1       /* I2C bit-banged       */
 286/* I2C speed and slave address */
 287#define CONFIG_SYS_I2C_SPEED            50000
 288#define CONFIG_SYS_I2C_SLAVE            0x7F
 289#define I2C_SOFT_DECLARATIONS
 290
 291/*
 292 * Software (bit-bang) I2C driver configuration
 293 */
 294#define I2C_BASE_DIR    ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
 295#define I2C_BASE_PORT   ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
 296
 297#define SDA_BIT         0x40
 298#define SCL_BIT         0x80
 299#define SDA_CONF        0x1000
 300#define SCL_CONF        0x2000
 301
 302#define I2C_ACTIVE      do {} while (0)
 303#define I2C_TRISTATE    do {} while (0)
 304#define I2C_READ        ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
 305#define I2C_SDA(bit)    if(bit) { \
 306                                clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
 307                        } else { \
 308                                clrbits(8, I2C_BASE_PORT, SDA_BIT); \
 309                                setbits(be16, I2C_BASE_DIR, SDA_CONF); \
 310                        }
 311#define I2C_SCL(bit)    if(bit) { \
 312                                clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
 313                        } else { \
 314                                clrbits(8, I2C_BASE_PORT, SCL_BIT); \
 315                                setbits(be16, I2C_BASE_DIR, SCL_CONF); \
 316                        }
 317#define I2C_DELAY       udelay(50)      /* 1/4 I2C clock duration */
 318
 319#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 320
 321/* I2C SYSMON (LM75, AD7414 is almost compatible)               */
 322#define CONFIG_DTT_LM75         1       /* ON Semi's LM75       */
 323#if defined(CONFIG_MGSUVD)
 324#define CONFIG_DTT_SENSORS      {0, 2, 4, 6}    /* Sensor addresses */
 325#else
 326#define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses */
 327#endif
 328#define CONFIG_SYS_DTT_MAX_TEMP 70
 329#define CONFIG_SYS_DTT_LOW_TEMP -30
 330#define CONFIG_SYS_DTT_HYSTERESIS       3
 331#define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 332#endif  /* __CONFIG_KM8XX_H */
 333