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30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34
35
36
37#define CONFIG_E300 1
38#define CONFIG_MPC83xx 1
39#define CONFIG_MPC834x 1
40#define CONFIG_MPC8349 1
41#define CONFIG_SBC8349 1
42
43#define CONFIG_SYS_TEXT_BASE 0xFF800000
44
45
46#undef CONFIG_MPC83XX_PCI2
47
48
49
50
51
52
53
54#ifdef CONFIG_PCI_33M
55#define CONFIG_83XX_CLKIN 33000000
56#else
57#define CONFIG_83XX_CLKIN 66000000
58#endif
59
60#ifndef CONFIG_SYS_CLK_FREQ
61#ifdef CONFIG_PCI_33M
62#define CONFIG_SYS_CLK_FREQ 33000000
63#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
64#else
65#define CONFIG_SYS_CLK_FREQ 66000000
66#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
67#endif
68#endif
69
70#undef CONFIG_BOARD_EARLY_INIT_F
71
72#define CONFIG_SYS_IMMR 0xE0000000
73
74#undef CONFIG_SYS_DRAM_TEST
75#define CONFIG_SYS_MEMTEST_START 0x00000000
76#define CONFIG_SYS_MEMTEST_END 0x00100000
77
78
79
80
81#undef CONFIG_DDR_ECC
82#undef CONFIG_DDR_ECC_CMD
83#define CONFIG_SPD_EEPROM
84#define CONFIG_SYS_83XX_DDR_USES_CS0
85
86
87
88
89
90
91
92
93
94
95
96#undef CONFIG_DDR_32BIT
97
98#define CONFIG_SYS_DDR_BASE 0x00000000
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
101#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
102 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
103#define CONFIG_DDR_2T_TIMING
104
105#if defined(CONFIG_SPD_EEPROM)
106
107
108
109#define SPD_EEPROM_ADDRESS 0x52
110
111#else
112
113
114
115
116#define CONFIG_SYS_DDR_SIZE 256
117#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
118#define CONFIG_SYS_DDR_TIMING_1 0x36332321
119#define CONFIG_SYS_DDR_TIMING_2 0x00000800
120#define CONFIG_SYS_DDR_CONTROL 0xc2000000
121#define CONFIG_SYS_DDR_INTERVAL 0x04060100
122
123#if defined(CONFIG_DDR_32BIT)
124
125#define CONFIG_SYS_DDR_MODE 0x00000023
126#else
127
128#define CONFIG_SYS_DDR_MODE 0x00000022
129#endif
130#endif
131
132
133
134
135#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000
136#define CONFIG_SYS_LBC_SDRAM_SIZE 128
137
138
139
140
141#define CONFIG_SYS_FLASH_CFI
142#define CONFIG_FLASH_CFI_DRIVER
143#define CONFIG_SYS_FLASH_BASE 0xFF800000
144#define CONFIG_SYS_FLASH_SIZE 8
145
146
147#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
148 (2 << BR_PS_SHIFT) | \
149 BR_V)
150
151#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7
152#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
153#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
154
155#define CONFIG_SYS_MAX_FLASH_BANKS 1
156#define CONFIG_SYS_MAX_FLASH_SECT 64
157
158#undef CONFIG_SYS_FLASH_CHECKSUM
159#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
160#define CONFIG_SYS_FLASH_WRITE_TOUT 500
161
162#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
163
164#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165#define CONFIG_SYS_RAMBOOT
166#else
167#undef CONFIG_SYS_RAMBOOT
168#endif
169
170#define CONFIG_SYS_INIT_RAM_LOCK 1
171#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
172#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
173
174#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176
177#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
178#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
179
180
181
182
183
184
185
186#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
187#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
188#define CONFIG_SYS_LBC_LBCR 0x00000000
189
190#undef CONFIG_SYS_LB_SDRAM
191
192#ifdef CONFIG_SYS_LB_SDRAM
193
194
195
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197
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199
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209
210
211
212#define CONFIG_SYS_BR2_PRELIM 0xF0001861
213#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
214#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019
215
216
217
218
219
220
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223
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225
226
227
228
229
230#define CONFIG_SYS_OR2_PRELIM 0xFC006901
231
232#define CONFIG_SYS_LBC_LSRT 0x32000000
233#define CONFIG_SYS_LBC_MRTPR 0x20000000
234
235#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \
236 | LSDMR_BSMA1516 \
237 | LSDMR_RFCR8 \
238 | LSDMR_PRETOACT6 \
239 | LSDMR_ACTTORW3 \
240 | LSDMR_BL8 \
241 | LSDMR_WRC3 \
242 | LSDMR_CL3 \
243 )
244
245
246
247
248#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
249#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
250#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
251#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
252#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
253#endif
254
255
256
257
258#define CONFIG_CONS_INDEX 1
259#define CONFIG_SYS_NS16550
260#define CONFIG_SYS_NS16550_SERIAL
261#define CONFIG_SYS_NS16550_REG_SIZE 1
262#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
263
264#define CONFIG_SYS_BAUDRATE_TABLE \
265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
266
267#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
268#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
269
270#define CONFIG_CMDLINE_EDITING 1
271#define CONFIG_AUTO_COMPLETE
272
273#define CONFIG_SYS_HUSH_PARSER
274#ifdef CONFIG_SYS_HUSH_PARSER
275#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
276#endif
277
278
279#define CONFIG_OF_LIBFDT 1
280#define CONFIG_OF_BOARD_SETUP 1
281#define CONFIG_OF_STDOUT_VIA_ALIAS 1
282
283
284#define CONFIG_HARD_I2C
285#undef CONFIG_SOFT_I2C
286#define CONFIG_FSL_I2C
287#define CONFIG_SYS_I2C_SPEED 400000
288#define CONFIG_SYS_I2C_SLAVE 0x7F
289#define CONFIG_SYS_I2C_NOPROBES {0x69}
290#define CONFIG_SYS_I2C1_OFFSET 0x3000
291#define CONFIG_SYS_I2C2_OFFSET 0x3100
292#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
293
294
295
296#define CONFIG_SYS_TSEC1_OFFSET 0x24000
297#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
298#define CONFIG_SYS_TSEC2_OFFSET 0x25000
299#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
300
301
302
303
304
305#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
306#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
307#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
308#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
309#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
310#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
311#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
312#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
313#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
314
315#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
316#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
317#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
318#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
319#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
320#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
321#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
322#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
323#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
324
325#if defined(CONFIG_PCI)
326
327#define PCI_64BIT
328#define PCI_ONE_PCI1
329#if defined(PCI_64BIT)
330#undef PCI_ALL_PCI1
331#undef PCI_TWO_PCI1
332#undef PCI_ONE_PCI1
333#endif
334
335#define CONFIG_NET_MULTI
336#define CONFIG_PCI_PNP
337
338#undef CONFIG_EEPRO100
339#undef CONFIG_TULIP
340
341#if !defined(CONFIG_PCI_PNP)
342 #define PCI_ENET0_IOADDR 0xFIXME
343 #define PCI_ENET0_MEMADDR 0xFIXME
344 #define PCI_IDSEL_NUMBER 0xFIXME
345#endif
346
347#undef CONFIG_PCI_SCAN_SHOW
348#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
349
350#endif
351
352
353
354
355#define CONFIG_TSEC_ENET
356
357#if defined(CONFIG_TSEC_ENET)
358#ifndef CONFIG_NET_MULTI
359#define CONFIG_NET_MULTI 1
360#endif
361
362#define CONFIG_TSEC1 1
363#define CONFIG_TSEC1_NAME "TSEC0"
364#define CONFIG_TSEC2 1
365#define CONFIG_TSEC2_NAME "TSEC1"
366#define CONFIG_PHY_BCM5421S 1
367#define TSEC1_PHY_ADDR 0x19
368#define TSEC2_PHY_ADDR 0x1a
369#define TSEC1_PHYIDX 0
370#define TSEC2_PHYIDX 0
371#define TSEC1_FLAGS TSEC_GIGABIT
372#define TSEC2_FLAGS TSEC_GIGABIT
373
374
375#define CONFIG_ETHPRIME "TSEC0"
376
377#endif
378
379
380
381
382#ifndef CONFIG_SYS_RAMBOOT
383 #define CONFIG_ENV_IS_IN_FLASH 1
384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
385 #define CONFIG_ENV_SECT_SIZE 0x20000
386 #define CONFIG_ENV_SIZE 0x2000
387
388
389#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
390#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
391
392#else
393 #define CONFIG_SYS_NO_FLASH 1
394 #define CONFIG_ENV_IS_NOWHERE 1
395 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
396 #define CONFIG_ENV_SIZE 0x2000
397#endif
398
399#define CONFIG_LOADS_ECHO 1
400#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
401
402
403
404
405
406#define CONFIG_BOOTP_BOOTFILESIZE
407#define CONFIG_BOOTP_BOOTPATH
408#define CONFIG_BOOTP_GATEWAY
409#define CONFIG_BOOTP_HOSTNAME
410
411
412
413
414
415#include <config_cmd_default.h>
416
417#define CONFIG_CMD_I2C
418#define CONFIG_CMD_MII
419#define CONFIG_CMD_PING
420
421#if defined(CONFIG_PCI)
422 #define CONFIG_CMD_PCI
423#endif
424
425#if defined(CONFIG_SYS_RAMBOOT)
426 #undef CONFIG_CMD_SAVEENV
427 #undef CONFIG_CMD_LOADS
428#endif
429
430
431#undef CONFIG_WATCHDOG
432
433
434
435
436#define CONFIG_SYS_LONGHELP
437#define CONFIG_SYS_LOAD_ADDR 0x2000000
438#define CONFIG_SYS_PROMPT "=> "
439
440#if defined(CONFIG_CMD_KGDB)
441 #define CONFIG_SYS_CBSIZE 1024
442#else
443 #define CONFIG_SYS_CBSIZE 256
444#endif
445
446#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
447#define CONFIG_SYS_MAXARGS 16
448#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
449#define CONFIG_SYS_HZ 1000
450
451
452
453
454
455
456#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
457
458#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
459
460#if 1
461#define CONFIG_SYS_HRCW_LOW (\
462 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
463 HRCWL_DDR_TO_SCB_CLK_1X1 |\
464 HRCWL_CSB_TO_CLKIN |\
465 HRCWL_VCO_1X2 |\
466 HRCWL_CORE_TO_CSB_2X1)
467#elif 0
468#define CONFIG_SYS_HRCW_LOW (\
469 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
470 HRCWL_DDR_TO_SCB_CLK_1X1 |\
471 HRCWL_CSB_TO_CLKIN |\
472 HRCWL_VCO_1X4 |\
473 HRCWL_CORE_TO_CSB_3X1)
474#elif 0
475#define CONFIG_SYS_HRCW_LOW (\
476 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
477 HRCWL_DDR_TO_SCB_CLK_1X1 |\
478 HRCWL_CSB_TO_CLKIN |\
479 HRCWL_VCO_1X4 |\
480 HRCWL_CORE_TO_CSB_2X1)
481#elif 0
482#define CONFIG_SYS_HRCW_LOW (\
483 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
484 HRCWL_DDR_TO_SCB_CLK_1X1 |\
485 HRCWL_CSB_TO_CLKIN |\
486 HRCWL_VCO_1X4 |\
487 HRCWL_CORE_TO_CSB_1X1)
488#elif 0
489#define CONFIG_SYS_HRCW_LOW (\
490 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
491 HRCWL_DDR_TO_SCB_CLK_1X1 |\
492 HRCWL_CSB_TO_CLKIN |\
493 HRCWL_VCO_1X4 |\
494 HRCWL_CORE_TO_CSB_1X1)
495#endif
496
497#if defined(PCI_64BIT)
498#define CONFIG_SYS_HRCW_HIGH (\
499 HRCWH_PCI_HOST |\
500 HRCWH_64_BIT_PCI |\
501 HRCWH_PCI1_ARBITER_ENABLE |\
502 HRCWH_PCI2_ARBITER_DISABLE |\
503 HRCWH_CORE_ENABLE |\
504 HRCWH_FROM_0X00000100 |\
505 HRCWH_BOOTSEQ_DISABLE |\
506 HRCWH_SW_WATCHDOG_DISABLE |\
507 HRCWH_ROM_LOC_LOCAL_16BIT |\
508 HRCWH_TSEC1M_IN_GMII |\
509 HRCWH_TSEC2M_IN_GMII )
510#else
511#define CONFIG_SYS_HRCW_HIGH (\
512 HRCWH_PCI_HOST |\
513 HRCWH_32_BIT_PCI |\
514 HRCWH_PCI1_ARBITER_ENABLE |\
515 HRCWH_PCI2_ARBITER_ENABLE |\
516 HRCWH_CORE_ENABLE |\
517 HRCWH_FROM_0X00000100 |\
518 HRCWH_BOOTSEQ_DISABLE |\
519 HRCWH_SW_WATCHDOG_DISABLE |\
520 HRCWH_ROM_LOC_LOCAL_16BIT |\
521 HRCWH_TSEC1M_IN_GMII |\
522 HRCWH_TSEC2M_IN_GMII )
523#endif
524
525
526#define CONFIG_SYS_SICRH 0
527#define CONFIG_SYS_SICRL SICRL_LDP_A
528
529#define CONFIG_SYS_HID0_INIT 0x000000000
530#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
531 HID0_ENABLE_INSTRUCTION_CACHE)
532
533
534
535
536
537
538
539#define CONFIG_SYS_HID2 HID2_HBE
540
541#define CONFIG_HIGH_BATS 1
542
543
544#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
545#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
546
547
548#ifdef CONFIG_PCI
549#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
550#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
551#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
552#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
553#else
554#define CONFIG_SYS_IBAT1L (0)
555#define CONFIG_SYS_IBAT1U (0)
556#define CONFIG_SYS_IBAT2L (0)
557#define CONFIG_SYS_IBAT2U (0)
558#endif
559
560#ifdef CONFIG_MPC83XX_PCI2
561#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
562#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
563#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
564#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
565#else
566#define CONFIG_SYS_IBAT3L (0)
567#define CONFIG_SYS_IBAT3U (0)
568#define CONFIG_SYS_IBAT4L (0)
569#define CONFIG_SYS_IBAT4U (0)
570#endif
571
572
573#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
574#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
575
576
577#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
578 BATL_GUARDEDSTORAGE)
579#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
580
581#define CONFIG_SYS_IBAT7L (0)
582#define CONFIG_SYS_IBAT7U (0)
583
584#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
585#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
586#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
587#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
588#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
589#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
590#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
591#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
592#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
593#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
594#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
595#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
596#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
597#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
598#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
599#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
600
601#if defined(CONFIG_CMD_KGDB)
602#define CONFIG_KGDB_BAUDRATE 230400
603#define CONFIG_KGDB_SER_INDEX 2
604#endif
605
606
607
608
609#define CONFIG_ENV_OVERWRITE
610
611#if defined(CONFIG_TSEC_ENET)
612#define CONFIG_HAS_ETH0
613#define CONFIG_HAS_ETH1
614#endif
615
616#define CONFIG_HOSTNAME SBC8349
617#define CONFIG_ROOTPATH /tftpboot/rootfs
618#define CONFIG_BOOTFILE uImage
619
620#define CONFIG_LOADADDR 800000
621
622#define CONFIG_BOOTDELAY 6
623#undef CONFIG_BOOTARGS
624
625#define CONFIG_BAUDRATE 115200
626
627#define CONFIG_EXTRA_ENV_SETTINGS \
628 "netdev=eth0\0" \
629 "hostname=sbc8349\0" \
630 "nfsargs=setenv bootargs root=/dev/nfs rw " \
631 "nfsroot=${serverip}:${rootpath}\0" \
632 "ramargs=setenv bootargs root=/dev/ram rw\0" \
633 "addip=setenv bootargs ${bootargs} " \
634 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
635 ":${hostname}:${netdev}:off panic=1\0" \
636 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
637 "flash_nfs=run nfsargs addip addtty;" \
638 "bootm ${kernel_addr}\0" \
639 "flash_self=run ramargs addip addtty;" \
640 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
641 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
642 "bootm\0" \
643 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
644 "update=protect off ff800000 ff83ffff; " \
645 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
646 "upd=run load update\0" \
647 "fdtaddr=780000\0" \
648 "fdtfile=sbc8349.dtb\0" \
649 ""
650
651#define CONFIG_NFSBOOTCOMMAND \
652 "setenv bootargs root=/dev/nfs rw " \
653 "nfsroot=$serverip:$rootpath " \
654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "tftp $loadaddr $bootfile;" \
657 "tftp $fdtaddr $fdtfile;" \
658 "bootm $loadaddr - $fdtaddr"
659
660#define CONFIG_RAMBOOTCOMMAND \
661 "setenv bootargs root=/dev/ram rw " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $ramdiskaddr $ramdiskfile;" \
664 "tftp $loadaddr $bootfile;" \
665 "tftp $fdtaddr $fdtfile;" \
666 "bootm $loadaddr $ramdiskaddr $fdtaddr"
667
668#define CONFIG_BOOTCOMMAND "run flash_self"
669
670#endif
671