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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38
39
40#ifdef CONFIG_CADDY2
41#define VME_CADDY2
42#endif
43
44
45
46
47#define CONFIG_E300 1
48#define CONFIG_MPC83xx 1
49#define CONFIG_MPC834x 1
50#define CONFIG_MPC8349 1
51#define CONFIG_VME8349 1
52
53#define CONFIG_SYS_TEXT_BASE 0xFFF00000
54
55#define CONFIG_MISC_INIT_R
56
57#define CONFIG_PCI
58
59#undef CONFIG_MPC83XX_PCI2
60
61#define CONFIG_PCI_66M
62#ifdef CONFIG_PCI_66M
63#define CONFIG_83XX_CLKIN 66000000
64#else
65#define CONFIG_83XX_CLKIN 33000000
66#endif
67
68#ifndef CONFIG_SYS_CLK_FREQ
69#ifdef CONFIG_PCI_66M
70#define CONFIG_SYS_CLK_FREQ 66000000
71#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
72#else
73#define CONFIG_SYS_CLK_FREQ 33000000
74#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
75#endif
76#endif
77
78#define CONFIG_SYS_IMMR 0xE0000000
79
80#undef CONFIG_SYS_DRAM_TEST
81#define CONFIG_SYS_MEMTEST_START 0x00000000
82#define CONFIG_SYS_MEMTEST_END 0x00100000
83
84
85
86
87#define CONFIG_DDR_ECC
88#define CONFIG_DDR_ECC_CMD
89#define CONFIG_SPD_EEPROM
90#define SPD_EEPROM_ADDRESS 0x54
91#define CONFIG_SYS_READ_SPD vme8349_read_spd
92#define CONFIG_SYS_83XX_DDR_USES_CS0
93
94
95
96
97
98
99
100
101
102
103
104#undef CONFIG_DDR_32BIT
105
106#define CONFIG_SYS_DDR_BASE 0x00000000
107#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
109#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
110 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
111#define CONFIG_DDR_2T_TIMING
112#define CONFIG_SYS_DDRCDR 0x80080001
113
114
115
116
117#define CONFIG_SYS_FLASH_CFI
118#define CONFIG_FLASH_CFI_DRIVER
119#ifdef VME_CADDY2
120#define CONFIG_SYS_FLASH_BASE 0xffc00000
121#define CONFIG_SYS_FLASH_SIZE 4
122#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
123 (2 << BR_PS_SHIFT) | \
124 BR_V)
125
126#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7
127#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015
129#else
130#define CONFIG_SYS_FLASH_BASE 0xf8000000
131#define CONFIG_SYS_FLASH_SIZE 128
132#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
133 (2 << BR_PS_SHIFT) | \
134 BR_V)
135
136#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7
137#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
138#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a
139#endif
140
141
142#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
143#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
144#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
145#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
146
147#define CONFIG_SYS_MAX_FLASH_BANKS 1
148#define CONFIG_SYS_MAX_FLASH_SECT 1024
149
150#undef CONFIG_SYS_FLASH_CHECKSUM
151#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500
153
154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
155
156#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
157#define CONFIG_SYS_RAMBOOT
158#else
159#undef CONFIG_SYS_RAMBOOT
160#endif
161
162#define CONFIG_SYS_INIT_RAM_LOCK 1
163#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000
164#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
165
166#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
167 GENERATED_GBL_DATA_SIZE)
168#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169
170#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
171#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
172
173
174
175
176
177
178
179#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
180#define CONFIG_SYS_LBC_LBCR 0x00000000
181
182#undef CONFIG_SYS_LB_SDRAM
183
184
185
186
187#define CONFIG_CONS_INDEX 1
188#define CONFIG_SYS_NS16550
189#define CONFIG_SYS_NS16550_SERIAL
190#define CONFIG_SYS_NS16550_REG_SIZE 1
191#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
192
193#define CONFIG_SYS_BAUDRATE_TABLE \
194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
195
196#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
197#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
198
199#define CONFIG_CMDLINE_EDITING
200#define CONFIG_AUTO_COMPLETE
201
202#define CONFIG_SYS_HUSH_PARSER
203#ifdef CONFIG_SYS_HUSH_PARSER
204#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
205#endif
206
207
208#define CONFIG_OF_LIBFDT
209#define CONFIG_OF_BOARD_SETUP
210#define CONFIG_OF_STDOUT_VIA_ALIAS
211
212
213#define CONFIG_I2C_MULTI_BUS
214#define CONFIG_HARD_I2C
215#undef CONFIG_SOFT_I2C
216#define CONFIG_FSL_I2C
217#define CONFIG_I2C_CMD_TREE
218#define CONFIG_SYS_I2C_SPEED 400000
219#define CONFIG_SYS_I2C_SLAVE 0x7F
220#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}}
221#define CONFIG_SYS_I2C1_OFFSET 0x3000
222#define CONFIG_SYS_I2C2_OFFSET 0x3100
223#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
224
225
226#define CONFIG_SYS_I2C_8574_ADDR2 0x20
227
228
229#define CONFIG_SYS_TSEC1_OFFSET 0x24000
230#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
231#define CONFIG_SYS_TSEC2_OFFSET 0x25000
232#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
233
234
235
236
237
238#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
239#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
240#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
241#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
242#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
243#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
244#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
245#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
246#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
247
248#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
249#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
250#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
251#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
252#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
253#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
254#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
255#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
256#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
257
258#if defined(CONFIG_PCI)
259
260#define PCI_64BIT
261#define PCI_ONE_PCI1
262#if defined(PCI_64BIT)
263#undef PCI_ALL_PCI1
264#undef PCI_TWO_PCI1
265#undef PCI_ONE_PCI1
266#endif
267
268#ifndef VME_CADDY2
269#define CONFIG_NET_MULTI
270#endif
271#define CONFIG_PCI_PNP
272
273#undef CONFIG_EEPRO100
274#undef CONFIG_TULIP
275
276#if !defined(CONFIG_PCI_PNP)
277 #define PCI_ENET0_IOADDR 0xFIXME
278 #define PCI_ENET0_MEMADDR 0xFIXME
279 #define PCI_IDSEL_NUMBER 0xFIXME
280#endif
281
282#define CONFIG_PCI_SCAN_SHOW
283#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
284
285#endif
286
287
288
289
290#ifdef VME_CADDY2
291#define CONFIG_E1000
292#else
293#define CONFIG_TSEC_ENET
294#endif
295
296#if defined(CONFIG_TSEC_ENET)
297#ifndef CONFIG_NET_MULTI
298#define CONFIG_NET_MULTI
299#endif
300
301#define CONFIG_GMII
302#define CONFIG_TSEC1
303#define CONFIG_TSEC1_NAME "TSEC0"
304#define CONFIG_TSEC2
305#define CONFIG_TSEC2_NAME "TSEC1"
306#define CONFIG_PHY_M88E1111
307#define TSEC1_PHY_ADDR 0x08
308#define TSEC2_PHY_ADDR 0x10
309#define TSEC1_PHYIDX 0
310#define TSEC2_PHYIDX 0
311#define TSEC1_FLAGS TSEC_GIGABIT
312#define TSEC2_FLAGS TSEC_GIGABIT
313
314
315#define CONFIG_ETHPRIME "TSEC0"
316
317#endif
318
319#if defined(CONFIG_E1000)
320#ifndef CONFIG_NET_MULTI
321#define CONFIG_NET_MULTI
322#endif
323#endif
324
325
326
327
328#ifndef CONFIG_SYS_RAMBOOT
329 #define CONFIG_ENV_IS_IN_FLASH
330 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
331 #define CONFIG_ENV_SECT_SIZE 0x20000
332 #define CONFIG_ENV_SIZE 0x2000
333
334
335#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
336#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
337
338#else
339 #define CONFIG_SYS_NO_FLASH
340 #define CONFIG_ENV_IS_NOWHERE
341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
342 #define CONFIG_ENV_SIZE 0x2000
343#endif
344
345#define CONFIG_LOADS_ECHO
346#define CONFIG_SYS_LOADS_BAUD_CHANGE
347
348
349
350
351#define CONFIG_BOOTP_BOOTFILESIZE
352#define CONFIG_BOOTP_BOOTPATH
353#define CONFIG_BOOTP_GATEWAY
354#define CONFIG_BOOTP_HOSTNAME
355
356
357
358
359#include <config_cmd_default.h>
360
361#define CONFIG_CMD_I2C
362#define CONFIG_CMD_MII
363#define CONFIG_CMD_PING
364#define CONFIG_CMD_DATE
365#define CONFIG_SYS_RTC_BUS_NUM 0x01
366#define CONFIG_SYS_I2C_RTC_ADDR 0x32
367#define CONFIG_RTC_RX8025
368#define CONFIG_CMD_TSI148
369
370#if defined(CONFIG_PCI)
371 #define CONFIG_CMD_PCI
372#endif
373
374#if defined(CONFIG_SYS_RAMBOOT)
375 #undef CONFIG_CMD_ENV
376 #undef CONFIG_CMD_LOADS
377#endif
378
379#define CONFIG_CMD_ELF
380
381#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
382
383#undef CONFIG_WATCHDOG
384
385
386
387
388#define CONFIG_SYS_LONGHELP
389#define CONFIG_SYS_LOAD_ADDR 0x2000000
390#define CONFIG_SYS_PROMPT "=> "
391
392#if defined(CONFIG_CMD_KGDB)
393 #define CONFIG_SYS_CBSIZE 1024
394#else
395 #define CONFIG_SYS_CBSIZE 256
396#endif
397
398#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
399#define CONFIG_SYS_MAXARGS 16
400#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
401#define CONFIG_SYS_HZ 1000
402
403
404
405
406
407
408#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
409
410#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
411
412#define CONFIG_SYS_HRCW_LOW (\
413 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
414 HRCWL_DDR_TO_SCB_CLK_1X1 |\
415 HRCWL_CSB_TO_CLKIN |\
416 HRCWL_VCO_1X2 |\
417 HRCWL_CORE_TO_CSB_2X1)
418
419#if defined(PCI_64BIT)
420#define CONFIG_SYS_HRCW_HIGH (\
421 HRCWH_PCI_HOST |\
422 HRCWH_64_BIT_PCI |\
423 HRCWH_PCI1_ARBITER_ENABLE |\
424 HRCWH_PCI2_ARBITER_DISABLE |\
425 HRCWH_CORE_ENABLE |\
426 HRCWH_FROM_0X00000100 |\
427 HRCWH_BOOTSEQ_DISABLE |\
428 HRCWH_SW_WATCHDOG_DISABLE |\
429 HRCWH_ROM_LOC_LOCAL_16BIT |\
430 HRCWH_TSEC1M_IN_GMII |\
431 HRCWH_TSEC2M_IN_GMII)
432#else
433#define CONFIG_SYS_HRCW_HIGH (\
434 HRCWH_PCI_HOST |\
435 HRCWH_32_BIT_PCI |\
436 HRCWH_PCI1_ARBITER_ENABLE |\
437 HRCWH_PCI2_ARBITER_ENABLE |\
438 HRCWH_CORE_ENABLE |\
439 HRCWH_FROM_0X00000100 |\
440 HRCWH_BOOTSEQ_DISABLE |\
441 HRCWH_SW_WATCHDOG_DISABLE |\
442 HRCWH_ROM_LOC_LOCAL_16BIT |\
443 HRCWH_TSEC1M_IN_GMII |\
444 HRCWH_TSEC2M_IN_GMII)
445#endif
446
447
448#define CONFIG_SYS_SICRH 0
449#define CONFIG_SYS_SICRL SICRL_LDP_A
450
451#define CONFIG_SYS_HID0_INIT 0x000000000
452#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
453 HID0_ENABLE_INSTRUCTION_CACHE)
454
455#define CONFIG_SYS_HID2 HID2_HBE
456
457#define CONFIG_SYS_GPIO1_PRELIM
458#define CONFIG_SYS_GPIO1_DIR 0x00100000
459#define CONFIG_SYS_GPIO1_DAT 0x00100000
460
461#define CONFIG_SYS_GPIO2_PRELIM
462#define CONFIG_SYS_GPIO2_DIR 0x78900000
463#define CONFIG_SYS_GPIO2_DAT 0x70100000
464
465#define CONFIG_HIGH_BATS
466
467
468#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
469 BATL_MEMCOHERENCE)
470#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
471 BATU_VS | BATU_VP)
472
473
474#ifdef CONFIG_PCI
475#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
476 BATL_MEMCOHERENCE)
477#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
478 BATU_VS | BATU_VP)
479#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
480 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
481#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
482 BATU_VS | BATU_VP)
483#else
484#define CONFIG_SYS_IBAT1L (0)
485#define CONFIG_SYS_IBAT1U (0)
486#define CONFIG_SYS_IBAT2L (0)
487#define CONFIG_SYS_IBAT2U (0)
488#endif
489
490#ifdef CONFIG_MPC83XX_PCI2
491#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
492 BATL_MEMCOHERENCE)
493#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
494 BATU_VS | BATU_VP)
495#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
496 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
497#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
498 BATU_VS | BATU_VP)
499#else
500#define CONFIG_SYS_IBAT3L (0)
501#define CONFIG_SYS_IBAT3U (0)
502#define CONFIG_SYS_IBAT4L (0)
503#define CONFIG_SYS_IBAT4U (0)
504#endif
505
506
507#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
508 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
509#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
510 BATU_VS | BATU_VP)
511
512#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
513#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
514
515#if (CONFIG_SYS_DDR_SIZE == 512)
516#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
517 BATL_PP_10 | BATL_MEMCOHERENCE)
518#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
519 BATU_BL_256M | BATU_VS | BATU_VP)
520#else
521#define CONFIG_SYS_IBAT7L (0)
522#define CONFIG_SYS_IBAT7U (0)
523#endif
524
525#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
526#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
527#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
528#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
529#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
530#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
531#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
532#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
533#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
534#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
535#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
536#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
537#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
538#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
539#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
540#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
541
542#if defined(CONFIG_CMD_KGDB)
543#define CONFIG_KGDB_BAUDRATE 230400
544#define CONFIG_KGDB_SER_INDEX 2
545#endif
546
547
548
549
550#define CONFIG_ENV_OVERWRITE
551
552#if defined(CONFIG_TSEC_ENET)
553#define CONFIG_HAS_ETH0
554#define CONFIG_HAS_ETH1
555#endif
556
557#define CONFIG_HOSTNAME VME8349
558#define CONFIG_ROOTPATH /tftpboot/rootfs
559#define CONFIG_BOOTFILE uImage
560
561#define CONFIG_LOADADDR 800000
562
563#define CONFIG_BOOTDELAY 6
564#undef CONFIG_BOOTARGS
565
566#define CONFIG_BAUDRATE 9600
567
568#define CONFIG_EXTRA_ENV_SETTINGS \
569 "netdev=eth0\0" \
570 "hostname=vme8349\0" \
571 "nfsargs=setenv bootargs root=/dev/nfs rw " \
572 "nfsroot=${serverip}:${rootpath}\0" \
573 "ramargs=setenv bootargs root=/dev/ram rw\0" \
574 "addip=setenv bootargs ${bootargs} " \
575 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
576 ":${hostname}:${netdev}:off panic=1\0" \
577 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
578 "flash_nfs=run nfsargs addip addtty;" \
579 "bootm ${kernel_addr}\0" \
580 "flash_self=run ramargs addip addtty;" \
581 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
582 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
583 "bootm\0" \
584 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
585 "update=protect off fff00000 fff3ffff; " \
586 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
587 "upd=run load update\0" \
588 "fdtaddr=780000\0" \
589 "fdtfile=vme8349.dtb\0" \
590 ""
591
592#define CONFIG_NFSBOOTCOMMAND \
593 "setenv bootargs root=/dev/nfs rw " \
594 "nfsroot=$serverip:$rootpath " \
595 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
596 "console=$consoledev,$baudrate $othbootargs;" \
597 "tftp $loadaddr $bootfile;" \
598 "tftp $fdtaddr $fdtfile;" \
599 "bootm $loadaddr - $fdtaddr"
600
601#define CONFIG_RAMBOOTCOMMAND \
602 "setenv bootargs root=/dev/ram rw " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "tftp $ramdiskaddr $ramdiskfile;" \
605 "tftp $loadaddr $bootfile;" \
606 "tftp $fdtaddr $fdtfile;" \
607 "bootm $loadaddr $ramdiskaddr $fdtaddr"
608
609#define CONFIG_BOOTCOMMAND "run flash_self"
610
611#ifndef __ASSEMBLY__
612int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
613 unsigned char *buffer, int len);
614#endif
615
616#endif
617