1/* 2 * (C) Copyright 2004-2005 3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 4 * 5 * (C) Copyright 2004 6 * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com 7 * 8 * (C) Copyright 2002 9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne 10 * 11 * (C) Copyright 2002 12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 13 * Marius Groeger <mgroeger@sysgo.de> 14 * 15 * Configuation settings for the xaeniax board. 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is free software; you can redistribute it and/or 21 * modify it under the terms of the GNU General Public License as 22 * published by the Free Software Foundation; either version 2 of 23 * the License, or (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 33 * MA 02111-1307 USA 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ 44#define CONFIG_XAENIAX 1 /* on a xaeniax board */ 45#define CONFIG_SYS_TEXT_BASE 0x0 46 47 48#define BOARD_LATE_INIT 1 49 50 51#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 52 53/* we will never enable dcache, because we have to setup MMU first */ 54#define CONFIG_SYS_NO_DCACHE 55 56/* 57 * select serial console configuration 58 */ 59#define CONFIG_PXA_SERIAL 60#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ 61 62 63/* allow to overwrite serial and ethaddr */ 64#define CONFIG_ENV_OVERWRITE 65 66#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 67 68#define CONFIG_BAUDRATE 115200 69 70#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ 71 72 73/* 74 * BOOTP options 75 */ 76#define CONFIG_BOOTP_BOOTFILESIZE 77#define CONFIG_BOOTP_BOOTPATH 78#define CONFIG_BOOTP_GATEWAY 79#define CONFIG_BOOTP_HOSTNAME 80 81 82/* 83 * Command line configuration. 84 */ 85#include <config_cmd_default.h> 86 87#define CONFIG_CMD_DHCP 88#define CONFIG_CMD_DIAG 89#define CONFIG_CMD_NFS 90#define CONFIG_CMD_SDRAM 91#define CONFIG_CMD_SNTP 92 93#undef CONFIG_CMD_DTT 94 95 96#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 97#define CONFIG_NETMASK 255.255.255.0 98#define CONFIG_IPADDR 192.168.68.201 99#define CONFIG_SERVERIP 192.168.68.62 100 101#define CONFIG_BOOTDELAY 3 102#define CONFIG_BOOTCOMMAND "bootm 0x00100000" 103#define CONFIG_BOOTARGS "console=ttyS1,115200" 104#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 105#define CONFIG_SETUP_MEMORY_TAGS 1 106#define CONFIG_INITRD_TAG 1 107 108#if defined(CONFIG_CMD_KGDB) 109#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ 110#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ 111#endif 112 113/* 114 * Size of malloc() pool; this lives below the uppermost 128 KiB which are 115 * used for the RAM copy of the uboot code 116 */ 117#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 118 119/* 120 * Miscellaneous configurable options 121 */ 122#define CONFIG_SYS_LONGHELP /* undef to save memory */ 123#define CONFIG_SYS_HUSH_PARSER 1 124 125#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 126 127#ifdef CONFIG_SYS_HUSH_PARSER 128#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ 129#else 130#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ 131#endif 132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 134#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 136#define CONFIG_SYS_DEVICE_NULLDEV 1 137 138#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 139#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 140 141#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ 142 143#define CONFIG_SYS_HZ 1000 144#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ 145 146/* 147 * Physical Memory Map 148 */ 149#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ 150#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 151#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 152#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 153#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 154#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 155#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 156#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 157#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 158 159#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 160#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 161#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 162#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 163#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 164 165#define CONFIG_SYS_DRAM_BASE 0xa0000000 166#define CONFIG_SYS_DRAM_SIZE 0x04000000 167 168#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 169 170#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 171#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) 172 173/* 174 * FLASH and environment organization 175 */ 176#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 178 179/* timeout values are in ticks */ 180#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 181#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 182 183/* FIXME */ 184#define CONFIG_ENV_IS_IN_FLASH 1 185#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ 186#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 187 188/* 189 * Stack sizes 190 * 191 * The stack sizes are set up in start.S using the settings below 192 */ 193#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 194#ifdef CONFIG_USE_IRQ 195#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 196#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 197#endif 198 199/* 200 * SMSC91C111 Network Card 201 */ 202#define CONFIG_NET_MULTI 203#define CONFIG_SMC91111 1 204#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ 205#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ 206#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ 207#undef CONFIG_SHOW_ACTIVITY 208#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ 209 210/* 211 * GPIO settings 212 */ 213 214/* 215 * GP05 == nUSBReset is 1 216 * GP10 == CFReset is 1 217 * GP13 == nCFDataEnable is 1 218 * GP14 == nCFAddrEnable is 1 219 * GP15 == nCS1 is 1 220 * GP21 == ComBrdReset is 1 221 * GP24 == SFRM is 1 222 * GP25 == TXD is 1 223 * GP31 == SYNC is 1 224 * GP33 == nCS5 is 1 225 * GP39 == FFTXD is 1 226 * GP41 == RTS is 1 227 * GP43 == BTTXD is 1 228 * GP45 == BTRTS is 1 229 * GP47 == TXD is 1 230 * GP48 == nPOE is 1 231 * GP49 == nPWE is 1 232 * GP50 == nPIOR is 1 233 * GP51 == nPIOW is 1 234 * GP52 == nPCE[1] is 1 235 * GP53 == nPCE[2] is 1 236 * GP54 == nPSKTSEL is 1 237 * GP55 == nPREG is 1 238 * GP78 == nCS2 is 1 239 * GP79 == nCS3 is 1 240 * GP80 == nCS4 is 1 241 * GP82 == NSSPSFRM is 1 242 * GP83 == NSSPTXD is 1 243 */ 244#define CONFIG_SYS_GPSR0_VAL 0x8320E420 245#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 246#define CONFIG_SYS_GPSR2_VAL 0x000DC000 247 248/* 249 * GP03 == LANReset is 0 250 * GP06 == USBWakeUp is 0 251 * GP11 == USBControl is 0 252 * GP12 == Buzzer is 0 253 * GP16 == PWM0 is 0 254 * GP17 == PWM1 is 0 255 * GP23 == SCLK is 0 256 * GP30 == SDATA_OUT is 0 257 * GP81 == NSSPCLK is 0 258 */ 259#define CONFIG_SYS_GPCR0_VAL 0x40C31848 260#define CONFIG_SYS_GPCR1_VAL 0x00000000 261#define CONFIG_SYS_GPCR2_VAL 0x00020000 262 263/* 264 * GP00 == CPUWakeUpUSB is input 265 * GP01 == GP reset is input 266 * GP02 == LANInterrupt is input 267 * GP03 == LANReset is output 268 * GP04 == USBInterrupt is input 269 * GP05 == nUSBReset is output 270 * GP06 == USBWakeUp is output 271 * GP07 == CFReady/nBusy is input 272 * GP08 == nCFCardDetect1 is input 273 * GP09 == nCFCardDetect2 is input 274 * GP10 == nCFReset is output 275 * GP11 == USBControl is output 276 * GP12 == Buzzer is output 277 * GP13 == CFDataEnable is output 278 * GP14 == CFAddressEnable is output 279 * GP15 == nCS1 is output 280 * GP16 == PWM0 is output 281 * GP17 == PWM1 is output 282 * GP18 == RDY is input 283 * GP19 == ReaderReady is input 284 * GP20 == ReaderReset is input 285 * GP21 == ComBrdReset is output 286 * GP23 == SCLK is output 287 * GP24 == SFRM is output 288 * GP25 == TXD is output 289 * GP26 == RXD is input 290 * GP27 == EXTCLK is input 291 * GP28 == BITCLK is output 292 * GP29 == SDATA_IN0 is input 293 * GP30 == SDATA_OUT is output 294 * GP31 == SYNC is output 295 * GP32 == SYSSCLK is output 296 * GP33 == nCS5 is output 297 * GP34 == FFRXD is input 298 * GP35 == CTS is input 299 * GP36 == DCD is input 300 * GP37 == DSR is input 301 * GP38 == RI is input 302 * GP39 == FFTXD is output 303 * GP40 == DTR is output 304 * GP41 == RTS is output 305 * GP42 == BTRXD is input 306 * GP43 == BTTXD is output 307 * GP44 == BTCTS is input 308 * GP45 == BTRTS is output 309 * GP46 == RXD is input 310 * GP47 == TXD is output 311 * GP48 == nPOE is output 312 * GP49 == nPWE is output 313 * GP50 == nPIOR is output 314 * GP51 == nPIOW is output 315 * GP52 == nPCE[1] is output 316 * GP53 == nPCE[2] is output 317 * GP54 == nPSKTSEL is output 318 * GP55 == nPREG is output 319 * GP56 == nPWAIT is input 320 * GP57 == nPIOS16 is input 321 * GP58 == LDD[0] is output 322 * GP59 == LDD[1] is output 323 * GP60 == LDD[2] is output 324 * GP61 == LDD[3] is output 325 * GP62 == LDD[4] is output 326 * GP63 == LDD[5] is output 327 * GP64 == LDD[6] is output 328 * GP65 == LDD[7] is output 329 * GP66 == LDD[8] is output 330 * GP67 == LDD[9] is output 331 * GP68 == LDD[10] is output 332 * GP69 == LDD[11] is output 333 * GP70 == LDD[12] is output 334 * GP71 == LDD[13] is output 335 * GP72 == LDD[14] is output 336 * GP73 == LDD[15] is output 337 * GP74 == LCD_FCLK is output 338 * GP75 == LCD_LCLK is output 339 * GP76 == LCD_PCLK is output 340 * GP77 == LCD_ACBIAS is output 341 * GP78 == nCS2 is output 342 * GP79 == nCS3 is output 343 * GP80 == nCS4 is output 344 * GP81 == NSSPCLK is output 345 * GP82 == NSSPSFRM is output 346 * GP83 == NSSPTXD is output 347 * GP84 == NSSPRXD is input 348 */ 349#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 350#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 351#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF 352 353/* 354 * GP01 == GP reset is AF01 355 * GP15 == nCS1 is AF10 356 * GP16 == PWM0 is AF10 357 * GP17 == PWM1 is AF10 358 * GP18 == RDY is AF01 359 * GP23 == SCLK is AF10 360 * GP24 == SFRM is AF10 361 * GP25 == TXD is AF10 362 * GP26 == RXD is AF01 363 * GP27 == EXTCLK is AF01 364 * GP28 == BITCLK is AF01 365 * GP29 == SDATA_IN0 is AF10 366 * GP30 == SDATA_OUT is AF01 367 * GP31 == SYNC is AF01 368 * GP32 == SYSCLK is AF01 369 * GP33 == nCS5 is AF10 370 * GP34 == FFRXD is AF01 371 * GP35 == CTS is AF01 372 * GP36 == DCD is AF01 373 * GP37 == DSR is AF01 374 * GP38 == RI is AF01 375 * GP39 == FFTXD is AF10 376 * GP40 == DTR is AF10 377 * GP41 == RTS is AF10 378 * GP42 == BTRXD is AF01 379 * GP43 == BTTXD is AF10 380 * GP44 == BTCTS is AF01 381 * GP45 == BTRTS is AF10 382 * GP46 == RXD is AF10 383 * GP47 == TXD is AF01 384 * GP48 == nPOE is AF10 385 * GP49 == nPWE is AF10 386 * GP50 == nPIOR is AF10 387 * GP51 == nPIOW is AF10 388 * GP52 == nPCE[1] is AF10 389 * GP53 == nPCE[2] is AF10 390 * GP54 == nPSKTSEL is AF10 391 * GP55 == nPREG is AF10 392 * GP56 == nPWAIT is AF01 393 * GP57 == nPIOS16 is AF01 394 * GP58 == LDD[0] is AF10 395 * GP59 == LDD[1] is AF10 396 * GP60 == LDD[2] is AF10 397 * GP61 == LDD[3] is AF10 398 * GP62 == LDD[4] is AF10 399 * GP63 == LDD[5] is AF10 400 * GP64 == LDD[6] is AF10 401 * GP65 == LDD[7] is AF10 402 * GP66 == LDD[8] is AF10 403 * GP67 == LDD[9] is AF10 404 * GP68 == LDD[10] is AF10 405 * GP69 == LDD[11] is AF10 406 * GP70 == LDD[12] is AF10 407 * GP71 == LDD[13] is AF10 408 * GP72 == LDD[14] is AF10 409 * GP73 == LDD[15] is AF10 410 * GP74 == LCD_FCLK is AF10 411 * GP75 == LCD_LCLK is AF10 412 * GP76 == LCD_PCLK is AF10 413 * GP77 == LCD_ACBIAS is AF10 414 * GP78 == nCS2 is AF10 415 * GP79 == nCS3 is AF10 416 * GP80 == nCS4 is AF10 417 * GP81 == NSSPCLK is AF01 418 * GP82 == NSSPSFRM is AF01 419 * GP83 == NSSPTXD is AF01 420 * GP84 == NSSPRXD is AF10 421 */ 422#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 423#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A 424#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 425#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA 426#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA 427#define CONFIG_SYS_GAFR2_U_VAL 0x00000256 428 429/* 430 * clock settings 431 */ 432/* RDH = 1 433 * PH = 0 434 * VFS = 0 435 * BFS = 0 436 * SSS = 0 437 */ 438#define CONFIG_SYS_PSSR_VAL 0x00000030 439 440#define CONFIG_SYS_CKEN 0x00000080 /* */ 441#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ 442#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 443 444 445/* 446 * Memory settings 447 * 448 * This is the configuration for nCS0/1 -> flash banks 449 * configuration for nCS1 : 450 * [31] 0 - 451 * [30:28] 000 - 452 * [27:24] 0000 - 453 * [23:20] 0000 - 454 * [19] 0 - 455 * [18:16] 000 - 456 * configuration for nCS0: 457 * [15] 0 - Slower Device 458 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns 459 * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns 460 * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) 461 * [03] 0 - 32 Bit bus width 462 * [02:00] 010 - burst OF 4 ROM or FLASH 463*/ 464#define CONFIG_SYS_MSC0_VAL 0x000023D2 465 466/* This is the configuration for nCS2/3 -> USB controller, LAN 467 * configuration for nCS3: LAN 468 * [31] 0 - Slower Device 469 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns 470 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns 471 * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns 472 * [19] 0 - 32 Bit bus width 473 * [18:16] 100 - variable latency I/O 474 * configuration for nCS2: USB 475 * [15] 1 - Faster Device 476 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 477 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 478 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 479 * [03] 1 - 16 Bit bus width 480 * [02:00] 100 - variable latency I/O 481 */ 482#define CONFIG_SYS_MSC1_VAL 0x1224A26C 483 484/* This is the configuration for nCS4/5 -> LAN 485 * configuration for nCS5: 486 * [31] 0 - 487 * [30:28] 000 - 488 * [27:24] 0000 - 489 * [23:20] 0000 - 490 * [19] 0 - 491 * [18:16] 000 - 492 * configuration for nCS4: LAN 493 * [15] 1 - Faster Device 494 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 495 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 496 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 497 * [03] 0 - 32 Bit bus width 498 * [02:00] 100 - variable latency I/O 499 */ 500#define CONFIG_SYS_MSC2_VAL 0x00001224 501 502/* MDCNFG: SDRAM Configuration Register 503 * 504 * [31:29] 000 - reserved 505 * [28] 0 - no SA1111 compatiblity mode 506 * [27] 0 - latch return data with return clock 507 * [26] 0 - alternate addressing for pair 2/3 508 * [25:24] 00 - timings 509 * [23] 0 - internal banks in lower partition 2/3 (not used) 510 * [22:21] 00 - row address bits for partition 2/3 (not used) 511 * [20:19] 00 - column address bits for partition 2/3 (not used) 512 * [18] 0 - SDRAM partition 2/3 width is 32 bit 513 * [17] 0 - SDRAM partition 3 disabled 514 * [16] 0 - SDRAM partition 2 disabled 515 * [15:13] 000 - reserved 516 * [12] 0 - no SA1111 compatiblity mode 517 * [11] 1 - latch return data with return clock 518 * [10] 0 - no alternate addressing for pair 0/1 519 * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk 520 * [7] 1 - 4 internal banks in lower partition pair 521 * [06:05] 10 - 13 row address bits for partition 0/1 522 * [04:03] 01 - 9 column address bits for partition 0/1 523 * [02] 0 - SDRAM partition 0/1 width is 32 bit 524 * [01] 0 - disable SDRAM partition 1 525 * [00] 1 - enable SDRAM partition 0 526 */ 527/* use the configuration above but disable partition 0 */ 528#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 529 530/* MDREFR: SDRAM Refresh Control Register 531 * 532 * [32:26] 0 - reserved 533 * [25] 0 - K2FREE: not free running 534 * [24] 0 - K1FREE: not free running 535 * [23] 0 - K0FREE: not free running 536 * [22] 0 - SLFRSH: self refresh disabled 537 * [21] 0 - reserved 538 * [20] 1 - APD: auto power down 539 * [19] 0 - K2DB2: SDCLK2 is MemClk 540 * [18] 0 - K2RUN: disable SDCLK2 541 * [17] 0 - K1DB2: SDCLK1 is MemClk 542 * [16] 1 - K1RUN: enable SDCLK1 543 * [15] 1 - E1PIN: SDRAM clock enable 544 * [14] 0 - K0DB2: SDCLK0 is MemClk 545 * [13] 0 - K0RUN: disable SDCLK0 546 * [12] 0 - E0PIN: disable SDCKE0 547 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 548 */ 549#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ 550 551/* MDMRS: Mode Register Set Configuration Register 552 * 553 * [31] 0 - reserved 554 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) 555 * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) 556 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) 557 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) 558 * [15] 0 - reserved 559 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. 560 * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. 561 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. 562 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. 563 */ 564#define CONFIG_SYS_MDMRS_VAL 0x00320032 565 566#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 567#define CONFIG_SYS_SXCNFG_VAL 0x00000000 568 569/* 570 * PCMCIA and CF Interfaces 571 */ 572#define CONFIG_SYS_MECR_VAL 0x00000000 573#define CONFIG_SYS_MCMEM0_VAL 0x00010504 574#define CONFIG_SYS_MCMEM1_VAL 0x00010504 575#define CONFIG_SYS_MCATT0_VAL 0x00010504 576#define CONFIG_SYS_MCATT1_VAL 0x00010504 577#define CONFIG_SYS_MCIO0_VAL 0x00004715 578#define CONFIG_SYS_MCIO1_VAL 0x00004715 579 580 581#endif /* __CONFIG_H */ 582