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26#ifndef __FSL_PMIC_H__
27#define __FSL_PMIC_H__
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36
37enum {
38 REG_INT_STATUS0 = 0,
39 REG_INT_MASK0,
40 REG_INT_SENSE0,
41 REG_INT_STATUS1,
42 REG_INT_MASK1,
43 REG_INT_SENSE1,
44 REG_PU_MODE_S,
45 REG_IDENTIFICATION,
46 REG_UNUSED0,
47 REG_ACC0,
48 REG_ACC1,
49 REG_UNUSED1,
50 REG_UNUSED2,
51 REG_POWER_CTL0,
52 REG_POWER_CTL1,
53 REG_POWER_CTL2,
54 REG_REGEN_ASSIGN,
55 REG_UNUSED3,
56 REG_MEM_A,
57 REG_MEM_B,
58 REG_RTC_TIME,
59 REG_RTC_ALARM,
60 REG_RTC_DAY,
61 REG_RTC_DAY_ALARM,
62 REG_SW_0,
63 REG_SW_1,
64 REG_SW_2,
65 REG_SW_3,
66 REG_SW_4,
67 REG_SW_5,
68 REG_SETTING_0,
69 REG_SETTING_1,
70 REG_MODE_0,
71 REG_MODE_1,
72 REG_POWER_MISC,
73 REG_UNUSED4,
74 REG_UNUSED5,
75 REG_UNUSED6,
76 REG_UNUSED7,
77 REG_UNUSED8,
78 REG_UNUSED9,
79 REG_UNUSED10,
80 REG_UNUSED11,
81 REG_ADC0,
82 REG_ADC1,
83 REG_ADC2,
84 REG_ADC3,
85 REG_ADC4,
86 REG_CHARGE,
87 REG_USB0,
88 REG_USB1,
89 REG_LED_CTL0,
90 REG_LED_CTL1,
91 REG_LED_CTL2,
92 REG_LED_CTL3,
93 REG_UNUSED12,
94 REG_UNUSED13,
95 REG_TRIM0,
96 REG_TRIM1,
97 REG_TEST0,
98 REG_TEST1,
99 REG_TEST2,
100 REG_TEST3,
101 REG_TEST4,
102};
103
104
105#define GPO1EN (1 << 6)
106#define GPO1STBY (1 << 7)
107#define GPO2EN (1 << 8)
108#define GPO2STBY (1 << 9)
109#define GPO3EN (1 << 10)
110#define GPO3STBY (1 << 11)
111#define GPO4EN (1 << 12)
112#define GPO4STBY (1 << 13)
113#define PWGT1SPIEN (1 << 15)
114#define PWGT2SPIEN (1 << 16)
115#define PWUP (1 << 21)
116
117
118#define COINCHEN (1 << 23)
119#define BATTDETEN (1 << 19)
120
121
122#define RTCRSTI (1 << 7)
123
124void pmic_show_pmic_info(void);
125void pmic_reg_write(u32 reg, u32 value);
126u32 pmic_reg_read(u32 reg);
127
128#endif
129