1/* 2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/************************************************************************* 25 * Altera Nios2 Standard Peripherals 26 ************************************************************************/ 27 28#ifndef __NIOS2IO_H__ 29#define __NIOS2IO_H__ 30 31/*------------------------------------------------------------------------ 32 * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) 33 *----------------------------------------------------------------------*/ 34typedef volatile struct nios_uart_t { 35 unsigned rxdata; /* Rx data reg */ 36 unsigned txdata; /* Tx data reg */ 37 unsigned status; /* Status reg */ 38 unsigned control; /* Control reg */ 39 unsigned divisor; /* Baud rate divisor reg */ 40 unsigned endofpacket; /* End-of-packet reg */ 41}nios_uart_t; 42 43/* status register */ 44#define NIOS_UART_PE (1 << 0) /* parity error */ 45#define NIOS_UART_FE (1 << 1) /* frame error */ 46#define NIOS_UART_BRK (1 << 2) /* break detect */ 47#define NIOS_UART_ROE (1 << 3) /* rx overrun */ 48#define NIOS_UART_TOE (1 << 4) /* tx overrun */ 49#define NIOS_UART_TMT (1 << 5) /* tx empty */ 50#define NIOS_UART_TRDY (1 << 6) /* tx ready */ 51#define NIOS_UART_RRDY (1 << 7) /* rx ready */ 52#define NIOS_UART_E (1 << 8) /* exception */ 53#define NIOS_UART_DCTS (1 << 10) /* cts change */ 54#define NIOS_UART_CTS (1 << 11) /* cts */ 55#define NIOS_UART_EOP (1 << 12) /* eop detected */ 56 57/* control register */ 58#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ 59#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ 60#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ 61#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ 62#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ 63#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ 64#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ 65#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ 66#define NIOS_UART_IE (1 << 8) /* exception int ena */ 67#define NIOS_UART_TBRK (1 << 9) /* transmit break */ 68#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ 69#define NIOS_UART_RTS (1 << 11) /* rts */ 70#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ 71 72 73/*------------------------------------------------------------------------ 74 * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) 75 *----------------------------------------------------------------------*/ 76typedef volatile struct nios_timer_t { 77 unsigned status; /* Timer status reg */ 78 unsigned control; /* Timer control reg */ 79 unsigned periodl; /* Timeout period low */ 80 unsigned periodh; /* Timeout period high */ 81 unsigned snapl; /* Snapshot low */ 82 unsigned snaph; /* Snapshot high */ 83}nios_timer_t; 84 85/* status register */ 86#define NIOS_TIMER_TO (1 << 0) /* Timeout */ 87#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ 88 89/* control register */ 90#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ 91#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ 92#define NIOS_TIMER_START (1 << 2) /* Start timer */ 93#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ 94 95 96/*------------------------------------------------------------------------ 97 * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) 98 *----------------------------------------------------------------------*/ 99typedef volatile struct nios_pio_t { 100 unsigned int data; /* Data value at each PIO in/out */ 101 unsigned int direction; /* Data direct. for each PIO bit */ 102 unsigned int interruptmask; /* Per-bit IRQ enable/disable */ 103 unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ 104}nios_pio_t; 105 106/* direction register */ 107#define NIOS_PIO_OUT (1) /* PIO bit is output */ 108#define NIOS_PIO_IN (0) /* PIO bit is input */ 109 110 111/*------------------------------------------------------------------------ 112 * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) 113 *----------------------------------------------------------------------*/ 114typedef volatile struct nios_spi_t { 115 unsigned rxdata; /* Rx data reg */ 116 unsigned txdata; /* Tx data reg */ 117 unsigned status; /* Status reg */ 118 unsigned control; /* Control reg */ 119 unsigned reserved; /* (master only) */ 120 unsigned slaveselect; /* SPI slave select mask (master only) */ 121}nios_spi_t; 122 123/* status register */ 124#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ 125#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ 126#define NIOS_SPI_TMT (1 << 5) /* tx empty */ 127#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ 128#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ 129#define NIOS_SPI_E (1 << 8) /* exception */ 130 131/* control register */ 132#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ 133#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ 134#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ 135#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ 136#define NIOS_SPI_IE (1 << 8) /* exception int ena */ 137#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ 138 139/*------------------------------------------------------------------------ 140 * JTAG UART 141 *----------------------------------------------------------------------*/ 142typedef volatile struct nios_jtag_t { 143 unsigned data; /* Data register */ 144 unsigned control; /* Control register */ 145}nios_jtag_t; 146 147/* data register */ 148#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ 149#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ 150#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ 151 152/* control register */ 153#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ 154#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ 155#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ 156#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ 157#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ 158#define NIOS_JTAG_RRDY (1 << 12) /* read available */ 159#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ 160 161/*------------------------------------------------------------------------ 162 * SYSTEM ID 163 *----------------------------------------------------------------------*/ 164typedef volatile struct nios_sysid_t { 165 unsigned id; /* The system build id*/ 166 unsigned timestamp; /* Timestamp */ 167}nios_sysid_t; 168 169#endif /* __NIOS2IO_H__ */ 170