1/* 2 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc 3 * Copyright (c) 2005 MontaVista Software 4 * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22#ifndef _EHCI_FSL_H 23#define _EHCI_FSL_H 24 25#include <asm/processor.h> 26 27/* Global offsets */ 28#define FSL_SKIP_PCI 0x100 29 30/* offsets for the non-ehci registers in the FSL SOC USB controller */ 31#define FSL_SOC_USB_ULPIVP 0x170 32#define FSL_SOC_USB_PORTSC1 0x184 33#define PORT_PTS_MSK (3 << 30) 34#define PORT_PTS_UTMI (0 << 30) 35#define PORT_PTS_ULPI (2 << 30) 36#define PORT_PTS_SERIAL (3 << 30) 37#define PORT_PTS_PTW (1 << 28) 38#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ 39#define PORT_PTS_PHCD (1 << 23) 40#define PORT_PP (1 << 12) 41#define PORT_PR (1 << 8) 42 43/* USBMODE Register bits */ 44#define CM_IDLE (0 << 0) 45#define CM_RESERVED (1 << 0) 46#define CM_DEVICE (2 << 0) 47#define CM_HOST (3 << 0) 48#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ 49#define USBMODE_RESERVED_2 (0 << 2) 50#define SLOM (1 << 3) 51#define SDIS (1 << 4) 52 53/* CONTROL Register bits */ 54#define ULPI_INT_EN (1 << 0) 55#define WU_INT_EN (1 << 1) 56#define USB_EN (1 << 2) 57#define LSF_EN (1 << 3) 58#define KEEP_OTG_ON (1 << 4) 59#define OTG_PORT (1 << 5) 60#define REFSEL_12MHZ (0 << 6) 61#define REFSEL_16MHZ (1 << 6) 62#define REFSEL_48MHZ (2 << 6) 63#define PLL_RESET (1 << 8) 64#define UTMI_PHY_EN (1 << 9) 65#define PHY_CLK_SEL_UTMI (0 << 10) 66#define PHY_CLK_SEL_ULPI (1 << 10) 67#define CLKIN_SEL_USB_CLK (0 << 11) 68#define CLKIN_SEL_USB_CLK2 (1 << 11) 69#define CLKIN_SEL_SYS_CLK (2 << 11) 70#define CLKIN_SEL_SYS_CLK2 (3 << 11) 71#define RESERVED_18 (0 << 13) 72#define RESERVED_17 (0 << 14) 73#define RESERVED_16 (0 << 15) 74#define WU_INT (1 << 16) 75#define PHY_CLK_VALID (1 << 17) 76 77#define FSL_SOC_USB_PORTSC2 0x188 78 79/* OTG Status Control Register bits */ 80#define FSL_SOC_USB_OTGSC 0x1a4 81#define CTRL_VBUS_DISCHARGE (0x1<<0) 82#define CTRL_VBUS_CHARGE (0x1<<1) 83#define CTRL_OTG_TERMINATION (0x1<<3) 84#define CTRL_DATA_PULSING (0x1<<4) 85#define CTRL_ID_PULL_EN (0x1<<5) 86#define HA_DATA_PULSE (0x1<<6) 87#define HA_BA (0x1<<7) 88#define STS_USB_ID (0x1<<8) 89#define STS_A_VBUS_VALID (0x1<<9) 90#define STS_A_SESSION_VALID (0x1<<10) 91#define STS_B_SESSION_VALID (0x1<<11) 92#define STS_B_SESSION_END (0x1<<12) 93#define STS_1MS_TOGGLE (0x1<<13) 94#define STS_DATA_PULSING (0x1<<14) 95#define INTSTS_USB_ID (0x1<<16) 96#define INTSTS_A_VBUS_VALID (0x1<<17) 97#define INTSTS_A_SESSION_VALID (0x1<<18) 98#define INTSTS_B_SESSION_VALID (0x1<<19) 99#define INTSTS_B_SESSION_END (0x1<<20) 100#define INTSTS_1MS (0x1<<21) 101#define INTSTS_DATA_PULSING (0x1<<22) 102#define INTR_USB_ID_EN (0x1<<24) 103#define INTR_A_VBUS_VALID_EN (0x1<<25) 104#define INTR_A_SESSION_VALID_EN (0x1<<26) 105#define INTR_B_SESSION_VALID_EN (0x1<<27) 106#define INTR_B_SESSION_END_EN (0x1<<28) 107#define INTR_1MS_TIMER_EN (0x1<<29) 108#define INTR_DATA_PULSING_EN (0x1<<30) 109#define INTSTS_MASK (0x00ff0000) 110 111/* USBCMD Bits of interest */ 112#define EHCI_FSL_USBCMD_RST (1 << 1) 113#define EHCI_FSL_USBCMD_RS (1 << 0) 114 115#define INTERRUPT_ENABLE_BITS_MASK \ 116 (INTR_USB_ID_EN | \ 117 INTR_1MS_TIMER_EN | \ 118 INTR_A_VBUS_VALID_EN | \ 119 INTR_A_SESSION_VALID_EN | \ 120 INTR_B_SESSION_VALID_EN | \ 121 INTR_B_SESSION_END_EN | \ 122 INTR_DATA_PULSING_EN) 123 124#define INTERRUPT_STATUS_BITS_MASK \ 125 (INTSTS_USB_ID | \ 126 INTR_1MS_TIMER_EN | \ 127 INTSTS_A_VBUS_VALID | \ 128 INTSTS_A_SESSION_VALID | \ 129 INTSTS_B_SESSION_VALID | \ 130 INTSTS_B_SESSION_END | \ 131 INTSTS_DATA_PULSING) 132 133#define FSL_SOC_USB_USBMODE 0x1a8 134 135#define USBGENCTRL 0x200 /* NOTE: big endian */ 136#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ 137#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ 138#define GC_PPP (1 << 3) /* Port Power Polarity */ 139#define GC_PFP (1 << 2) /* Power Fault Polarity */ 140#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ 141#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ 142 143#define ISIPHYCTRL 0x204 /* NOTE: big endian */ 144#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ 145#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ 146#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ 147#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ 148#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ 149 150#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 151#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 152#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 153#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 154#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 155#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 156#define SNOOP_SIZE_2GB 0x1e 157 158/* System Clock Control Register */ 159#define MPC83XX_SCCR_USB_MASK 0x00f00000 160#define MPC83XX_SCCR_USB_DRCM_11 0x00300000 161#define MPC83XX_SCCR_USB_DRCM_01 0x00100000 162#define MPC83XX_SCCR_USB_DRCM_10 0x00200000 163 164#if defined(CONFIG_MPC83xx) 165#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR 166#elif defined(CONFIG_MPC85xx) 167#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR 168#elif defined(CONFIG_MPC512X) 169#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR 170#endif 171 172/* 173 * USB Registers 174 */ 175struct usb_ehci { 176 u32 id; /* 0x000 - Identification register */ 177 u32 hwgeneral; /* 0x004 - General hardware parameters */ 178 u32 hwhost; /* 0x008 - Host hardware parameters */ 179 u32 hwdevice; /* 0x00C - Device hardware parameters */ 180 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ 181 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ 182 u8 res1[0x68]; 183 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ 184 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ 185 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ 186 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ 187 u32 sbuscfg; /* 0x090 - System Bus Interface Control */ 188 u8 res2[0x6C]; 189 u16 caplength; /* 0x100 - Capability Register Length */ 190 u16 hciversion; /* 0x102 - Host Interface Version */ 191 u32 hcsparams; /* 0x104 - Host Structural Parameters */ 192 u32 hccparams; /* 0x108 - Host Capability Parameters */ 193 u8 res3[0x14]; 194 u32 dciversion; /* 0x120 - Device Interface Version */ 195 u32 dciparams; /* 0x124 - Device Controller Params */ 196 u8 res4[0x18]; 197 u32 usbcmd; /* 0x140 - USB Command */ 198 u32 usbsts; /* 0x144 - USB Status */ 199 u32 usbintr; /* 0x148 - USB Interrupt Enable */ 200 u32 frindex; /* 0x14C - USB Frame Index */ 201 u8 res5[0x4]; 202 u32 perlistbase; /* 0x154 - Periodic List Base 203 - USB Device Address */ 204 u32 ep_list_addr; /* 0x158 - Next Asynchronous List 205 - End Point Address */ 206 u8 res6[0x4]; 207 u32 burstsize; /* 0x160 - Programmable Burst Size */ 208#define FSL_EHCI_TXPBURST(X) ((X) << 8) 209#define FSL_EHCI_RXPBURST(X) (X) 210 u32 txfilltuning; /* 0x164 - Host TT Transmit 211 pre-buffer packet tuning */ 212 u8 res7[0x8]; 213 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ 214 u8 res8[0xc]; 215 u32 config_flag; /* 0x180 - Configured Flag Register */ 216 u32 portsc; /* 0x184 - Port status/control */ 217 u8 res9[0x1C]; 218 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ 219 u32 usbmode; /* 0x1a8 - USB Device Mode */ 220 u32 epsetupstat; /* 0x1ac - End Point Setup Status */ 221 u32 epprime; /* 0x1b0 - End Point Init Status */ 222 u32 epflush; /* 0x1b4 - End Point De-initlialize */ 223 u32 epstatus; /* 0x1b8 - End Point Status */ 224 u32 epcomplete; /* 0x1bc - End Point Complete */ 225 u32 epctrl0; /* 0x1c0 - End Point Control 0 */ 226 u32 epctrl1; /* 0x1c4 - End Point Control 1 */ 227 u32 epctrl2; /* 0x1c8 - End Point Control 2 */ 228 u32 epctrl3; /* 0x1cc - End Point Control 3 */ 229 u32 epctrl4; /* 0x1d0 - End Point Control 4 */ 230 u32 epctrl5; /* 0x1d4 - End Point Control 5 */ 231 u8 res10[0x28]; 232 u32 usbgenctrl; /* 0x200 - USB General Control */ 233 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ 234 u8 res11[0x1F8]; 235 u32 snoop1; /* 0x400 - Snoop 1 */ 236 u32 snoop2; /* 0x404 - Snoop 2 */ 237 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ 238 u32 prictrl; /* 0x40c - Priority Control */ 239 u32 sictrl; /* 0x410 - System Interface Control */ 240 u8 res12[0xEC]; 241 u32 control; /* 0x500 - Control */ 242 u8 res13[0xafc]; 243}; 244 245#endif /* _EHCI_FSL_H */ 246