uboot/board/gdsys/405ep/dlvision-10g.c
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   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <command.h>
  26#include <asm/processor.h>
  27#include <asm/io.h>
  28#include <asm/ppc4xx-gpio.h>
  29
  30#include <gdsys_fpga.h>
  31
  32#include "../common/osd.h"
  33
  34enum {
  35        UNITTYPE_VIDEO_USER = 0,
  36        UNITTYPE_MAIN_USER = 1,
  37        UNITTYPE_VIDEO_SERVER = 2,
  38        UNITTYPE_MAIN_SERVER = 3,
  39};
  40
  41enum {
  42        HWVER_101 = 0,
  43        HWVER_110 = 1,
  44};
  45
  46enum {
  47        AUDIO_NONE = 0,
  48        AUDIO_TX = 1,
  49        AUDIO_RX = 2,
  50        AUDIO_RXTX = 3,
  51};
  52
  53enum {
  54        SYSCLK_156250 = 2,
  55};
  56
  57enum {
  58        RAM_NONE = 0,
  59        RAM_DDR2_32 = 1,
  60        RAM_DDR2_64 = 2,
  61};
  62
  63static void print_fpga_info(unsigned dev)
  64{
  65        ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  66        u16 versions = in_le16(&fpga->versions);
  67        u16 fpga_version = in_le16(&fpga->fpga_version);
  68        u16 fpga_features = in_le16(&fpga->fpga_features);
  69        unsigned unit_type;
  70        unsigned hardware_version;
  71        unsigned feature_compression;
  72        unsigned feature_rs232;
  73        unsigned feature_audio;
  74        unsigned feature_sysclock;
  75        unsigned feature_ramconfig;
  76        unsigned feature_carrier_speed;
  77        unsigned feature_carriers;
  78        unsigned feature_video_channels;
  79        int fpga_state = get_fpga_state(dev);
  80
  81        printf("FPGA%d: ", dev);
  82
  83        hardware_version = versions & 0x000f;
  84
  85        if (fpga_state
  86            && !((hardware_version == HWVER_101)
  87                 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
  88                puts("not available\n");
  89                print_fpga_state(dev);
  90                return;
  91        }
  92
  93        unit_type = (versions >> 4) & 0x000f;
  94        hardware_version = versions & 0x000f;
  95        feature_compression = (fpga_features >> 13) & 0x0003;
  96        feature_rs232 = fpga_features & (1<<11);
  97        feature_audio = (fpga_features >> 9) & 0x0003;
  98        feature_sysclock = (fpga_features >> 7) & 0x0003;
  99        feature_ramconfig = (fpga_features >> 5) & 0x0003;
 100        feature_carrier_speed = fpga_features & (1<<4);
 101        feature_carriers = (fpga_features >> 2) & 0x0003;
 102        feature_video_channels = fpga_features & 0x0003;
 103
 104        switch (unit_type) {
 105        case UNITTYPE_VIDEO_USER:
 106                printf("Videochannel Userside");
 107                break;
 108
 109        case UNITTYPE_MAIN_USER:
 110                printf("Mainchannel Userside");
 111                break;
 112
 113        case UNITTYPE_VIDEO_SERVER:
 114                printf("Videochannel Serverside");
 115                break;
 116
 117        case UNITTYPE_MAIN_SERVER:
 118                printf("Mainchannel Serverside");
 119                break;
 120
 121        default:
 122                printf("UnitType %d(not supported)", unit_type);
 123                break;
 124        }
 125
 126        switch (hardware_version) {
 127        case HWVER_101:
 128                printf(" HW-Ver 1.01\n");
 129                break;
 130
 131        case HWVER_110:
 132                printf(" HW-Ver 1.10\n");
 133                break;
 134
 135        default:
 136                printf(" HW-Ver %d(not supported)\n",
 137                       hardware_version);
 138                break;
 139        }
 140
 141        printf("       FPGA V %d.%02d, features:",
 142                fpga_version / 100, fpga_version % 100);
 143
 144        printf(" %sRS232", feature_rs232 ? "" : "no ");
 145
 146        switch (feature_audio) {
 147        case AUDIO_NONE:
 148                printf(", no audio");
 149                break;
 150
 151        case AUDIO_TX:
 152                printf(", audio tx");
 153                break;
 154
 155        case AUDIO_RX:
 156                printf(", audio rx");
 157                break;
 158
 159        case AUDIO_RXTX:
 160                printf(", audio rx+tx");
 161                break;
 162
 163        default:
 164                printf(", audio %d(not supported)", feature_audio);
 165                break;
 166        }
 167
 168        switch (feature_sysclock) {
 169        case SYSCLK_156250:
 170                printf(", clock 156.25 MHz");
 171                break;
 172
 173        default:
 174                printf(", clock %d(not supported)", feature_sysclock);
 175                break;
 176        }
 177
 178        puts(",\n       ");
 179
 180        switch (feature_ramconfig) {
 181        case RAM_NONE:
 182                printf("no RAM");
 183                break;
 184
 185        case RAM_DDR2_32:
 186                printf("RAM 32 bit DDR2");
 187                break;
 188
 189        case RAM_DDR2_64:
 190                printf("RAM 64 bit DDR2");
 191                break;
 192
 193        default:
 194                printf("RAM %d(not supported)", feature_ramconfig);
 195                break;
 196        }
 197
 198        printf(", %d carrier(s) %s", feature_carriers,
 199                feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 200
 201        printf(", %d video channel(s)\n", feature_video_channels);
 202}
 203
 204/*
 205 * Check Board Identity:
 206 */
 207int checkboard(void)
 208{
 209        unsigned k;
 210        char *s = getenv("serial#");
 211
 212        printf("Board: ");
 213
 214        printf("DLVision 10G");
 215
 216        if (s != NULL) {
 217                puts(", serial# ");
 218                puts(s);
 219        }
 220
 221        puts("\n");
 222
 223        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
 224                print_fpga_info(k);
 225
 226        return 0;
 227}
 228
 229int last_stage_init(void)
 230{
 231        unsigned k;
 232
 233        for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
 234                if (!get_fpga_state(k)
 235                    || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
 236                        osd_probe(k);
 237
 238        return 0;
 239}
 240