1/* 2 * (C) Copyright 2001 3 * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef _HYMOD_H_ 25#define _HYMOD_H_ 26 27#include <linux/config.h> 28#ifdef CONFIG_8260 29#include <asm/iopin_8260.h> 30#endif 31 32/* 33 * hymod configuration data - passed by boot code via the board information 34 * structure (only U-Boot has support for this at the moment) 35 * 36 * there are three types of data passed up from the boot monitor. the first 37 * (type hymod_eeprom_t) is the eeprom data that was read off both the main 38 * (or mother) board and the mezzanine board (if any). this data defines how 39 * many Xilinx fpgas are on each board, and their types (among other things). 40 * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where 41 * in the physical address space the various Xilinx fpga access regions have 42 * been mapped by the boot rom. the third type of data (type xlx_iopins_t, 43 * one per Xilinx fpga) defines which io port pins are connected to the various 44 * signals required to program a Xilinx fpga. 45 * 46 * A ram/flash "bank" refers to memory controlled by the same chip select. 47 * 48 * the eeprom contents are defined as in technical note #2 - basically, 49 * a header, zero or more records in no particular order, and a 32 bit crc 50 * a record is 1 or more type bytes, a length byte and "length" bytes. 51 */ 52 53#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ 54#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ 55#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ 56 57/* eeprom header */ 58typedef 59 struct { 60 unsigned char id; /* eeprom id byte */ 61 unsigned char :1; 62 unsigned char ver:7; /* eeprom contents version number */ 63 unsigned long len; /* total # of bytes btw hdr and crc */ 64 } 65hymod_eehdr_t; 66 67/* maximum number of bytes available for eeprom data records */ 68#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ 69 - sizeof (hymod_eehdr_t) \ 70 - sizeof (unsigned long)) 71 72/* eeprom data record */ 73typedef 74 union { 75 struct { 76 unsigned char topbit:1; 77 unsigned char type:7; 78 unsigned char len; 79 unsigned char data[1]; /* variable length */ 80 } small; 81 struct { 82 unsigned short topbit:1; 83 unsigned short nxtbit:1; 84 unsigned short type:14; 85 unsigned short len; 86 unsigned char data[1]; /* variable length */ 87 } medium; 88 struct { 89 unsigned long topbit:1; 90 unsigned long nxtbit:1; 91 unsigned long type:30; 92 unsigned long len; 93 unsigned char data[1]; /* variable length */ 94 } large; 95 } 96hymod_eerec_t; 97 98#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ 99#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ 100 101/* eeprom record types */ 102#define HYMOD_EEREC_SERNO 1 /* serial number */ 103#define HYMOD_EEREC_DATE 2 /* date */ 104#define HYMOD_EEREC_BATCH 3 /* batch id */ 105#define HYMOD_EEREC_TYPE 4 /* board type */ 106#define HYMOD_EEREC_REV 5 /* revision number */ 107#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ 108#define HYMOD_EEREC_FLASH 7 /* flash sizes */ 109#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ 110#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ 111#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ 112#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ 113#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ 114#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ 115#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ 116#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ 117#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ 118#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ 119#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ 120#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ 121 122/* some dimensions */ 123#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ 124#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ 125#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ 126#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ 127#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ 128 129#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ 130 131/* board types */ 132#define HYMOD_BDTYPE_NONE 0 /* information not present */ 133#define HYMOD_BDTYPE_IO 1 /* I/O main board */ 134#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ 135#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ 136#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ 137#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ 138#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ 139#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ 140 141/* Xilinx fpga types */ 142#define HYMOD_XTYP_NONE 0 /* information not present */ 143#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ 144#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ 145#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ 146#define HYMOD_XTYP_MAX 4 /* first invalid value */ 147 148/* Xilinx fpga speeds */ 149#define HYMOD_XSPD_NONE 0 /* information not present */ 150#define HYMOD_XSPD_SIX 1 151#define HYMOD_XSPD_SEVEN 2 152#define HYMOD_XSPD_EIGHT 3 153#define HYMOD_XSPD_MAX 4 /* first invalid value */ 154 155/* Xilinx fpga temperatures */ 156#define HYMOD_XTMP_NONE 0 /* information not present */ 157#define HYMOD_XTMP_COM 1 158#define HYMOD_XTMP_IND 2 159#define HYMOD_XTMP_MAX 3 /* first invalid value */ 160 161/* Xilinx fpga grades */ 162#define HYMOD_XTMP_NONE 0 /* information not present */ 163#define HYMOD_XTMP_NORMAL 1 164#define HYMOD_XTMP_ENGSAMP 2 165#define HYMOD_XTMP_MAX 3 /* first invalid value */ 166 167/* CPU types */ 168#define HYMOD_CPUTYPE_NONE 0 /* information not present */ 169#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ 170#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ 171 172/* CPU/BUS/CPM clock speeds */ 173#define HYMOD_CLKSPD_NONE 0 /* information not present */ 174#define HYMOD_CLKSPD_33MHZ 1 175#define HYMOD_CLKSPD_66MHZ 2 176#define HYMOD_CLKSPD_100MHZ 3 177#define HYMOD_CLKSPD_133MHZ 4 178#define HYMOD_CLKSPD_166MHZ 5 179#define HYMOD_CLKSPD_200MHZ 6 180#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ 181 182/* high speed serial chip types */ 183#define HYMOD_HSSTYPE_NONE 0 /* information not present */ 184#define HYMOD_HSSTYPE_AMCC52064 1 185#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ 186 187/* a date (yyyy-mm-dd) */ 188typedef 189 struct { 190 unsigned short year; 191 unsigned char month; 192 unsigned char day; 193 } 194hymod_date_t; 195 196/* describes a Xilinx fpga */ 197typedef 198 struct { 199 unsigned char type; /* chip type */ 200 unsigned char speed; /* chip speed rating */ 201 unsigned char temp; /* chip temperature rating */ 202 unsigned char grade; /* chip grade */ 203 } 204hymod_xlx_t; 205 206/* describes a Motorola embedded processor */ 207typedef 208 struct { 209 unsigned char type; /* CPU type */ 210 unsigned char cpuspd; /* speed of the PowerPC core */ 211 unsigned char busspd; /* speed of the system and 60x bus */ 212 unsigned char cpmspd; /* speed of the CPM co-processor */ 213 } 214hymod_mpc_t; 215 216/* info about high-speed (1Gbit) serial interface */ 217typedef 218 struct { 219 unsigned char type; /* high-speed serial chip type */ 220 unsigned char nchin; /* number of input channels mounted */ 221 unsigned char nchout; /* number of output channels mounted */ 222 } 223hymod_hss_t; 224 225/* 226 * this defines the contents of the serial eeprom that exists on every 227 * hymod board, including mezzanine boards (the serial eeprom will be 228 * faked for early development boards that don't have one) 229 */ 230 231typedef 232 struct { 233 unsigned char valid:1; /* contents of this struct is valid */ 234 unsigned char ver:7; /* eeprom contents version */ 235 unsigned char bdtype; /* board type */ 236 unsigned char bdrev; /* board revision */ 237 unsigned char batchlen; /* length of batch string below */ 238 unsigned long serno; /* serial number */ 239 hymod_date_t date; /* manufacture date */ 240 unsigned char batch[32]; /* manufacturer specific batch id */ 241 unsigned char nsdram; /* # of ram "banks" */ 242 unsigned char nflash; /* # of flash "banks" */ 243 unsigned char nzbt; /* # of ZBT rams */ 244 unsigned char nxlx; /* # of Xilinx fpgas */ 245 unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ 246 unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ 247 unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ 248 hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ 249 hymod_mpc_t mpc; /* Motorola MPC CPU info */ 250 hymod_hss_t hss; /* high-speed serial info */ 251 } 252hymod_eeprom_t; 253 254/* 255 * this defines a region in the processor's physical address space 256 */ 257typedef 258 struct { 259 unsigned long exists:1; /* 1 if the region exists, 0 if not */ 260 unsigned long size:31; /* size in bytes */ 261 unsigned long base; /* base address */ 262 } 263xlx_prgn_t; 264 265/* 266 * this defines where the various Xilinx fpga access regions are mapped 267 * into the physical address space of the processor 268 */ 269typedef 270 struct { 271 xlx_prgn_t prog; /* program access region */ 272 xlx_prgn_t reg; /* register access region */ 273 xlx_prgn_t port; /* port access region */ 274 } 275xlx_mmap_t; 276 277/* 278 * this defines which 8260 i/o port pins are connected to the various 279 * signals required for programming a Xilinx fpga 280 */ 281typedef 282 struct { 283 iopin_t prog_pin; /* assert for >= 300ns to program */ 284 iopin_t init_pin; /* goes high when fpga is cleared */ 285 iopin_t done_pin; /* goes high when program is done */ 286 iopin_t enable_pin; /* some fpgas need enabling */ 287 } 288xlx_iopins_t; 289 290/* all info about one Xilinx chip */ 291typedef 292 struct { 293 xlx_mmap_t mmap; 294 xlx_iopins_t iopins; 295 unsigned long irq:8; /* h/w intr req number for this fpga */ 296 } 297xlx_info_t; 298 299/* all info about one hymod board */ 300typedef 301 struct { 302 hymod_eeprom_t eeprom; 303 xlx_info_t xlx[HYMOD_MAX_XLX]; 304 } 305hymod_board_t; 306 307/* 308 * this defines the configuration information of a hymod board-set 309 * (main board + possible mezzanine board). In future, there may be 310 * more than one mezzanine board (stackable?) - if so, add a "mezz2" 311 * field, and so on... or make mezz an array? 312 */ 313typedef 314 struct { 315 unsigned long ver:8; /* version control */ 316 hymod_board_t main; /* main board info */ 317 hymod_board_t mezz; /* mezzanine board info */ 318 unsigned long crc; /* ensures kernel and boot prom agree */ 319 } 320hymod_conf_t; 321 322#endif /* _HYMOD_H_ */ 323