LXR uboot/board/mpl/pati/pati.h

   1/*
   2 * (C) Copyright 2003
   3 * Denis Peter, d.peter@mpl.ch
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22/************************************************************************
  23 * MACROS and register definitions for PATI Registers
  24 ************************************************************************/
  25#ifndef __PATI_H_
  26#define __PATI_H_       1
  27
  28#define PLD_PART_ID             0x0
  29#define PLD_BOARD_TIMING        0x4
  30#define PLD_CONF_REG1           0x8
  31#define PLD_CONF_REG2           0xC
  32#define PLD_CONF_RES            0x10
  33
  34#define SET_REG_BIT(y,x) (y<<(31-x))
  35#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
  36
  37/* SDRAM Controller PLD_PART_ID */
  38/* 9  10 11 12 13 14 19 31 */
  39#define SDRAM_PART3     9
  40#define SDRAM_PART2     10
  41#define SDRAM_PART1     11
  42#define SDRAM_PART0     12
  43#define SDRAM_ID3       13
  44#define SDRAM_ID2       14
  45#define SDRAM_ID1       19
  46#define SDRAM_ID0       31
  47
  48#define SDRAM_PART(x)   (       \
  49        (GET_REG_BIT(x,SDRAM_PART3)<<3) |\
  50        (GET_REG_BIT(x,SDRAM_PART2)<<2) |\
  51        (GET_REG_BIT(x,SDRAM_PART1)<<1) |\
  52        (GET_REG_BIT(x,SDRAM_PART0)))
  53
  54#define SDRAM_ID(x)     (       \
  55        (GET_REG_BIT(x,SDRAM_ID3)<<3) |\
  56        (GET_REG_BIT(x,SDRAM_ID2)<<2) |\
  57        (GET_REG_BIT(x,SDRAM_ID1)<<1) |\
  58        (GET_REG_BIT(x,SDRAM_ID0)))
  59
  60/* System Controller */
  61/* 0  1 3 4 5 16 20 28 29 30 */
  62#define SYSCNTR_PART4   0
  63#define SYSCNTR_PART3   1
  64#define SYSCNTR_PART2   3
  65#define SYSCNTR_PART1   4
  66#define SYSCNTR_PART0   5
  67#define SYSCNTR_ID4     16
  68#define SYSCNTR_ID3     20
  69#define SYSCNTR_ID2     28
  70#define SYSCNTR_ID1     29
  71#define SYSCNTR_ID0     30
  72
  73#define SYSCNTR_PART(x) (       \
  74        (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
  75        (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
  76        (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
  77        (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
  78        (GET_REG_BIT(x,SYSCNTR_PART0)))
  79
  80#define SYSCNTR_ID(x)   (       \
  81        (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
  82        (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
  83        (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
  84        (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
  85        (GET_REG_BIT(x,SYSCNTR_ID0)))
  86
  87/* SDRAM Controller PLD_BOARD_TIMING */
  88/* 9  10 11 12 13 14 19 31 */
  89#define SDRAM_CAL       9
  90#define SDRAM_RCD       10
  91#define SDRAM_WREQ      11
  92#define SDRAM_PR        12
  93#define SDRAM_RC        13
  94#define SDRAM_LMR       14
  95#define SDRAM_IIP       19
  96#define SDRAM_RES0      31
  97/* System Controller */
  98/* 0  1 3 4 5 16 20 28 29 30 */
  99#define SYSCNTR_BREV0   0
 100#define SYSCNTR_BREV1   1
 101#define SYSCNTR_BREV2   3
 102#define SYSCNTR_BREV3   4
 103#define SYSCNTR_RES0    5
 104#define SYSCNTR_RES1    16
 105#define SYSCNTR_RES2    20
 106#define SYSCNTR_FLWAIT2 28
 107#define SYSCNTR_FLWAIT1 29
 108#define SYSCNTR_FLWAIT0 30
 109
 110#define SYSCNTR_BREV(x) (       \
 111        (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
 112        (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
 113        (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
 114        (GET_REG_BIT(x,SYSCNTR_BREV0)))
 115
 116#define GET_SYSCNTR_FLWAIT(x)   (       \
 117        (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
 118        (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
 119        (GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
 120
 121#define SET_SYSCNTR_FLWAIT(x)   (       \
 122        (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
 123        (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
 124        (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
 125
 126/* SDRAM Controller REG 2*/
 127/* 9  10 11 12 13 14 19 31 */
 128#define SDRAM_MUX0      9
 129#define SDRAM_MUX1      10
 130#define SDRAM_PDIS      11
 131#define SDRAM_RES1      12
 132#define SDRAM_RES2      13
 133#define SDRAM_RES3      14
 134#define SDRAM_RES4      19
 135#define SDRAM_RIP       31
 136
 137#define GET_SDRAM_MUX(x)        (       \
 138        (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
 139        (GET_REG_BIT(x,SDRAM_MUX0)))
 140
 141
 142/* System Controller */
 143/* 0  1 3 4 5 16 20 28 29 30 */
 144#define SYSCNTR_FLAG    0
 145#define SYSCNTR_IP      1
 146#define SYSCNTR_BIND2   3
 147#define SYSCNTR_BIND1   4
 148#define SYSCNTR_BIND0   5
 149#define SYSCNTR_PRM     16
 150#define SYSCNTR_ICW     20
 151#define SYSCNTR_ISB2    28
 152#define SYSCNTR_ISB1    29
 153#define SYSCNTR_ISB0    30
 154
 155#define GET_SYSCNTR_BOOTIND(x)  (       \
 156        (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
 157        (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
 158        (GET_REG_BIT(x,SYSCNTR_BIND0)))
 159
 160#define SET_SYSCNTR_BOOTIND(x)  (       \
 161        (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
 162        (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
 163        (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
 164
 165#define GET_SYSCNTR_ISB(x)      (       \
 166        (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
 167        (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
 168        (GET_REG_BIT(x,SYSCNTR_ISB0)))
 169
 170#define SET_SYSCNTR_ISB(x)      (       \
 171        (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
 172        (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
 173        (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
 174
 175/* SDRAM Controller REG 3*/
 176/* 9  10 11 12 13 14 19 31 */
 177#define SDRAM_RES5      9
 178#define SDRAM_CFG1      10
 179#define SDRAM_CFG2      11
 180#define SDRAM_CFG3      12
 181#define SDRAM_RES6      13
 182#define SDRAM_CFG5      14
 183#define SDRAM_CFG6      19
 184#define SDRAM_RES7      31
 185
 186#define GET_SDRAM_CFG(x)        (       \
 187        (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
 188        (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
 189        (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
 190        (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
 191        (GET_REG_BIT(x,SDRAM_CFG1)))
 192
 193/* System Controller */
 194/* 0  1 3 4 5 16 20 28 29 30 */
 195#define SYSCNTR_BDIS    0
 196#define SYSCNTR_PCIM    1
 197#define SYSCNTR_CFG0    3
 198#define SYSCNTR_CFG1    4
 199#define SYSCNTR_CFG2    5
 200#define SYSCNTR_CFG3    16
 201#define SYSCNTR_BOOTEN  20
 202#define SYSCNTR_CPU_VPP 28
 203#define SYSCNTR_FL_VPP  29
 204#define SYSCNTR_FL_WP   30
 205
 206#define GET_SYSCNTR_CFG(x)      (       \
 207        (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
 208        (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
 209        (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
 210        (GET_REG_BIT(x,SYSCNTR_CFG0)))
 211
 212
 213/***************************************************************
 214 * MISC Defines
 215 ***************************************************************/
 216
 217#define PCI_VENDOR_ID_MPL       0x18E6
 218#define PCI_DEVICE_ID_PATI      0x00DA
 219
 220#if defined(CONFIG_MIP405)
 221#define PATI_FIRMWARE_START_OFFSET      0x00300000
 222#define PATI_ISO_STRING  "MEV-10084-001"
 223#endif
 224
 225#define PATI_ENDIAN_MODE        0x3E
 226
 227/*******************************************
 228 * PATI Mapping:
 229 * -------------
 230 * PCI Map:
 231 * -------
 232 * All addreses are mapped into the memory area
 233 * (IO Area on some areas may also be possible)
 234 * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
 235 * - pci_space0_addr:  configurable
 236 * - pci_space1_addr      configurable
 237 *
 238 * Local Map:
 239 * ----------
 240 * Local addresses (Remap)
 241 * - SDRAM      0x06000000 Size 16MByte mask 0xff000000
 242 * - EPLD CFG   0x07000000 Size 512Bytes
 243 * - FLASH      0x03000000 Size up to 8MByte
 244 * - CPU        0x01000000 Size 4MByte (only accessable if special configured)
 245 *
 246 * Implemention:
 247 * -------------
 248 * To prevent using large resources reservation on the host following
 249 * PCI mapping is choosed:
 250 * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
 251 * - pci_space0_addr:  configured to the EPLD Config Area size 256Bytes
 252 * - pci_space1_addr:  configured to the SDRAM Area size 1MBytes, this
 253 *                     space is used to switch between SDRAM, Flash and CPU
 254 *
 255 */
 256
 257/* Attribute definitions */
 258#define PATI_BUS_SIZE_8         0
 259#define PATI_BUS_SIZE_16        1
 260#define PATI_BUS_SIZE_32        3
 261
 262#define PATI_SPACE0_MASK        (0xFEFFFE00)  /* Mask Attributes */
 263#define PATI_SPACE1_MASK        (0x00000000)  /* Mask Attributes */
 264
 265#define PATI_EXTRA_LONG_EEPROM  1
 266
 267#define SPACE0_TA_ENABLE (1<<6)
 268#define SPACE1_TA_ENABLE (1<<6)
 269
 270/* Config Area */
 271#define PATI_LOC_CFG_ADDR               0x07000000              /* Local Address */
 272#define PATI_LOC_CFG_MASK               0xFFFFFF00              /* 256 Bytes */
 273/* Attributes */
 274#define PATI_LOC_CFG_BUS_SIZE           PATI_BUS_SIZE_32        /* 32 Bit */
 275#define PATI_LOC_CFG_BURST              0                       /* No Burst */
 276#define PATI_LOC_CFG_NO_PREFETCH        1                       /* No Prefetch */
 277#define PATI_LOC_CFG_TA_ENABLE          1                       /* Enable TA */
 278
 279#define PATI_LOC_CFG_SPACE0_ATTR  ( \
 280                PATI_LOC_CFG_BUS_SIZE | \
 281                (PATI_LOC_CFG_TA_ENABLE << 6) | \
 282                (PATI_LOC_CFG_NO_PREFETCH << 8) | \
 283                (PATI_LOC_CFG_BURST << 24) | \
 284                (PATI_EXTRA_LONG_EEPROM << 25))
 285
 286/* should never be used */
 287#define PATI_LOC_CFG_SPACE1_ATTR  ( \
 288                PATI_LOC_CFG_BUS_SIZE | \
 289                (PATI_LOC_CFG_TA_ENABLE << 6) | \
 290                (PATI_LOC_CFG_NO_PREFETCH << 9) | \
 291                (PATI_LOC_CFG_BURST << 8))
 292
 293
 294/* SDRAM Area */
 295#define PATI_LOC_SDRAM_ADDR             0x06000000              /* Local Address */
 296#define PATI_LOC_SDRAM_MASK             0xFFF00000              /* 1MByte */
 297/* Attributes */
 298#define PATI_LOC_SDRAM_BUS_SIZE         PATI_BUS_SIZE_32        /* 32 Bit */
 299#define PATI_LOC_SDRAM_BURST            0                       /* No Burst */
 300#define PATI_LOC_SDRAM_NO_PREFETCH      0                       /* Prefetch */
 301#define PATI_LOC_SDRAM_TA_ENABLE        1                       /* Enable TA */
 302
 303/* should never be used */
 304#define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
 305                PATI_LOC_SDRAM_BUS_SIZE | \
 306                (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
 307                (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
 308                (PATI_LOC_SDRAM_BURST << 24) | \
 309                (PATI_EXTRA_LONG_EEPROM << 25))
 310
 311#define PATI_LOC_SDRAM_SPACE1_ATTR  ( \
 312                PATI_LOC_SDRAM_BUS_SIZE | \
 313                (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
 314                (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
 315                (PATI_LOC_SDRAM_BURST << 8))
 316
 317
 318/* Flash Area */
 319#define PATI_LOC_FLASH_ADDR             0x03000000              /* Local Address */
 320#define PATI_LOC_FLASH_MASK             0xFFF00000              /* 1MByte */
 321/* Attributes */
 322#define PATI_LOC_FLASH_BUS_SIZE         PATI_BUS_SIZE_16        /* 16 Bit */
 323#define PATI_LOC_FLASH_BURST            0                       /* No Burst */
 324#define PATI_LOC_FLASH_NO_PREFETCH      1                       /* No Prefetch */
 325#define PATI_LOC_FLASH_TA_ENABLE        1                       /* Enable TA */
 326
 327/* should never be used */
 328#define PATI_LOC_FLASH_SPACE0_ATTR  ( \
 329                PATI_LOC_FLASH_BUS_SIZE | \
 330                (PATI_LOC_FLASH_TA_ENABLE << 6) | \
 331                (PATI_LOC_FLASH_NO_PREFETCH << 8) | \
 332                (PATI_LOC_FLASH_BURST << 24) | \
 333                (PATI_EXTRA_LONG_EEPROM << 25))
 334
 335#define PATI_LOC_FLASH_SPACE1_ATTR  ( \
 336                PATI_LOC_FLASH_BUS_SIZE | \
 337                (PATI_LOC_FLASH_TA_ENABLE << 6) | \
 338                (PATI_LOC_FLASH_NO_PREFETCH << 9) | \
 339                (PATI_LOC_FLASH_BURST << 8))
 340
 341
 342/* CPU Area */
 343#define PATI_LOC_CPU_ADDR               0x01000000              /* Local Address */
 344#define PATI_LOC_CPU_MASK               0xFFF00000              /* 1Mbyte */
 345/* Attributes */
 346#define PATI_LOC_CPU_BUS_SIZE           PATI_BUS_SIZE_32        /* 32 Bit */
 347#define PATI_LOC_CPU_BURST              0                       /* No Burst */
 348#define PATI_LOC_CPU_NO_PREFETCH        1                       /* No Prefetch */
 349#define PATI_LOC_CPU_TA_ENABLE          1                       /* Enable TA */
 350
 351/* should never be used */
 352#define PATI_LOC_CPU_SPACE0_ATTR  ( \
 353                PATI_LOC_CPU_BUS_SIZE | \
 354                (PATI_LOC_CPU_TA_ENABLE << 6) | \
 355                (PATI_LOC_CPU_NO_PREFETCH << 8) | \
 356                (PATI_LOC_CPU_BURST << 24) | \
 357                (PATI_EXTRA_CPU_EEPROM << 25))
 358
 359#define PATI_LOC_CPU_SPACE1_ATTR  ( \
 360                PATI_LOC_CPU_BUS_SIZE | \
 361                (PATI_LOC_CPU_TA_ENABLE << 6) | \
 362                (PATI_LOC_CPU_NO_PREFETCH << 9) | \
 363                (PATI_LOC_CPU_BURST << 8))
 364
 365/***************************************************
 366 * Hardware Config word definition
 367 ***************************************************/
 368#define BOOT_EXT_FLASH          0x00000000
 369#define BOOT_INT_FLASH          0x00000004
 370#define BOOT_FROM_PCI           0x00000006
 371#define BOOT_FROM_SDRAM         0x00000005
 372
 373#define ENABLE_INT_ARB          0x00000008
 374
 375#define INITIAL_IRQ_PREF        0x00000010
 376
 377#define INITIAL_MEM_0M          0x00000000
 378#define INITIAL_MEM_4M          0x00000080
 379#define INITIAL_MEM_8M          0x00000040
 380#define INITIAL_MEM_12M         0x000000C0
 381#define INITIAL_MEM_16M         0x00000020
 382#define INITIAL_MEM_20M         0x000000A0
 383#define INITIAL_MEM_24M         0x00000060
 384#define INITIAL_MEM_28M         0x000000E0
 385/* CONF */
 386#define INTERNAL_HWCONF         0x00000100
 387/* PRPM */
 388#define LOCAL_CPU_SLAVE         0x00000200
 389/* BDIS */
 390#define DISABLE_MEM_CNTR        0x00000400
 391/* PCIM */
 392#define PCI_MASTER_ONLY         0x00000800
 393
 394
 395#define PATI_HW_START           ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
 396#define PATI_HW_PCI_ONLY        ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
 397#define PATI_HW_CPU_ACC         ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
 398#define PATI_HW_CPU_SLAVE       ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
 399
 400/***************************************************
 401 * Direct Master Config
 402 ***************************************************/
 403#define PATI_DMASTER_PCI_ADDR           0x01000000
 404#define PATI_BUS_MASTER 1
 405
 406
 407#define PATI_DMASTER_MASK               0xFFF00000  /* 1MByte */
 408#define PATI_DMASTER_ADDR               0x01000000  /* Local Address */
 409
 410#define PATI_DMASTER_MEMORY_EN          0x00000001 /* 0x00000001 */
 411#define PATI_DMASTER_READ_AHEAD         0x00000004 /* 0x00000004 */
 412#define PATI_DMASTER_READ_NOT_AHEAD     0x00000000 /* 0x00000004 */
 413#define PATI_DMASTER_PRE_SIZE_CNTRL_0   0x00000000
 414#define PATI_DMASTER_PRE_SIZE_CNTRL_4   0x00000008
 415#define PATI_DMASTER_PRE_SIZE_CNTRL_8   0x00001000
 416#define PATI_DMASTER_PRE_SIZE_CNTRL_16  0x00001008
 417#define PATI_DMASTER_REL_PCI            0x00000000
 418#define PATI_DMASTER_NOT_REL_PCI        0x00000010
 419#define PATI_DMASTER_WR_INVAL           0x00000200
 420#define PATI_DMASTER_NOT_WR_INVAL       0x00000000
 421#define PATI_DMASTER_PRE_LIMIT          0x00000800
 422#define PATI_DMASTER_PRE_CONT           0x00000000
 423#define PATI_DMASTER_DELAY_WR_0         0x00000000
 424#define PATI_DMASTER_DELAY_WR_4         0x00004000
 425#define PATI_DMASTER_DELAY_WR_8         0x00008000
 426#define PATI_DMASTER_DELAY_WR_16        0x0000C000
 427
 428#define PATI_DMASTER_PCI_ADDR_MASK      0xFFFF0000
 429
 430#define PATI_DMASTER_ATTR       \
 431        PATI_DMASTER_MEMORY_EN | \
 432        PATI_DMASTER_READ_AHEAD | \
 433        PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
 434        PATI_DMASTER_REL_PCI | \
 435        PATI_DMASTER_NOT_WR_INVAL | \
 436        PATI_DMASTER_PRE_LIMIT | \
 437        PATI_DMASTER_DELAY_WR_0
 438
 439
 440#endif /* #ifndef __PATI_H_ */
 441