LXR uboot/board/mx1ads/mx1ads.c

   1/*
   2 * board/mx1ads/mx1ads.c
   3 *
   4 * (c) Copyright 2004
   5 * Techware Information Technology, Inc.
   6 * http://www.techware.com.tw/
   7 *
   8 * Ming-Len Wu <minglen_wu@techware.com.tw>
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <common.h>
  27#include <netdev.h>
  28/*#include <mc9328.h>*/
  29#include <asm/arch/imx-regs.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33#define FCLK_SPEED 1
  34
  35#if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
  36#define M_MDIV  0xC3
  37#define M_PDIV  0x4
  38#define M_SDIV  0x1
  39#elif FCLK_SPEED==1             /* Fout = 202.8MHz */
  40#define M_MDIV  0xA1
  41#define M_PDIV  0x3
  42#define M_SDIV  0x1
  43#endif
  44
  45#define USB_CLOCK 1
  46
  47#if USB_CLOCK==0
  48#define U_M_MDIV        0xA1
  49#define U_M_PDIV        0x3
  50#define U_M_SDIV        0x1
  51#elif USB_CLOCK==1
  52#define U_M_MDIV        0x48
  53#define U_M_PDIV        0x3
  54#define U_M_SDIV        0x2
  55#endif
  56
  57#if 0
  58
  59static inline void delay (unsigned long loops)
  60{
  61        __asm__ volatile ("1:\n"
  62                          "subs %0, %1, #1\n"
  63                          "bne 1b":"=r" (loops):"0" (loops));
  64}
  65
  66#endif
  67
  68/*
  69 * Miscellaneous platform dependent initialisations
  70 */
  71
  72void SetAsynchMode (void)
  73{
  74        __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
  75                 "mov r2, #0xC0000000 \n"
  76                 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
  77}
  78
  79static u32 mc9328sid;
  80
  81int board_init (void)
  82{
  83        volatile unsigned int tmp;
  84
  85        mc9328sid = SIDR;
  86
  87        GPCR = 0x000003AB;      /* I/O pad driving strength     */
  88
  89        /*      MX1_CS1U        = 0x00000A00;   */ /* SRAM initialization          */
  90/*      MX1_CS1L        = 0x11110601;   */
  91
  92        MPCTL0 = 0x04632410;    /* setting for 150 MHz MCU PLL CLK      */
  93
  94/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
  95 * BCLK divider to 2 (i.e. BCLK to 48 MHz)
  96 */
  97        CSCR = 0xAF000403;
  98
  99        CSCR |= 0x00200000;     /* Trigger the restart bit(bit 21)      */
 100        CSCR &= 0xFFFF7FFF;     /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
 101
 102/* setup cs4 for cs8900 ethernet */
 103
 104        CS4U = 0x00000F00;      /* Initialize CS4 for CS8900 ethernet   */
 105        CS4L = 0x00001501;
 106
 107        GIUS (0) &= 0xFF3FFFFF;
 108        GPR (0) &= 0xFF3FFFFF;
 109
 110        tmp = *(unsigned int *) (0x1500000C);
 111        tmp = *(unsigned int *) (0x1500000C);
 112
 113        SetAsynchMode ();
 114
 115        gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
 116
 117        gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
 118
 119        icache_enable ();
 120        dcache_enable ();
 121
 122/* set PERCLKs                          */
 123        PCDR = 0x00000055;      /* set PERCLKS                          */
 124
 125/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
 126 * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
 127 * all sources selected as normal interrupt
 128 */
 129
 130/*      MX1_INTTYPEH = 0;
 131        MX1_INTTYPEL = 0;
 132*/
 133        return 0;
 134}
 135
 136int board_late_init (void)
 137{
 138
 139        setenv ("stdout", "serial");
 140        setenv ("stderr", "serial");
 141
 142        switch (mc9328sid) {
 143        case 0x0005901d:
 144                printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
 145                        mc9328sid);
 146                break;
 147        case 0x04d4c01d:
 148                printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
 149                        mc9328sid);
 150                break;
 151        case 0x00d4c01d:
 152                printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
 153                        mc9328sid);
 154                break;
 155
 156        default:
 157                printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
 158                        mc9328sid);
 159                break;
 160        }
 161        return 0;
 162}
 163
 164int dram_init (void)
 165{
 166        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 167        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 168
 169        return 0;
 170}
 171
 172#ifdef CONFIG_CMD_NET
 173int board_eth_init(bd_t *bis)
 174{
 175        int rc = 0;
 176#ifdef CONFIG_CS8900
 177        rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
 178#endif
 179        return rc;
 180}
 181#endif
 182