1/* 2 * (C) Copyright 2000 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2001 7 * Advent Networks, Inc. <http://www.adventnetworks.com> 8 * Jay Monkman <jtm@smoothsmoothie.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29#include <common.h> 30#include <ioports.h> 31#include <mpc8260.h> 32#include "rpxsuper.h" 33 34/* 35 * I/O Port configuration table 36 * 37 * if conf is 1, then that port pin will be configured at boot time 38 * according to the five values podr/pdir/ppar/psor/pdat for that entry 39 */ 40 41const iop_conf_t iop_conf_tab[4][32] = { 42 43 /* Port A configuration */ 44 { /* conf ppar psor pdir podr pdat */ 45 /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ 46 /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ 47 /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ 48 /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ 49 /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ 50 /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ 51 /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ 52 /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ 53 /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ 54 /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ 55 /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ 56 /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ 57 /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ 58 /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ 59 /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ 60 /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ 61 /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ 62 /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ 63 /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ 64 /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ 65 /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ 66 /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ 67 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ 68 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ 69 /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ 70 /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ 71 /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ 72 /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ 73 /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ 74 /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ 75 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ 76 /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ 77 }, 78 79 /* Port B configuration */ 80 { /* conf ppar psor pdir podr pdat */ 81 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 82 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 83 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 84 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 85 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 86 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 87 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 88 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 89 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 90 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 91 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 92 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 93 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 94 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 95 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ 96 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ 97 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ 98 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ 99 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ 100 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ 101 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ 102 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ 103 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ 104 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ 105 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ 106 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ 107 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ 108 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ 109 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 110 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 111 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 112 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 113 }, 114 115 /* Port C */ 116 { /* conf ppar psor pdir podr pdat */ 117 /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ 118 /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ 119 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 120 /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ 121 /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ 122 /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ 123 /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ 124 /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ 125 /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 126 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 127 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 128 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 129 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ 130 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ 131 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ 132 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ 133 /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ 134 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 135 /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ 136 /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ 137 /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ 138 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ 139 /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ 140 /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ 141 /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ 142 /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ 143 /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ 144 /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ 145 /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ 146 /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ 147 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 148 /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ 149 }, 150 151 /* Port D */ 152 { /* conf ppar psor pdir podr pdat */ 153 /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 154 /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ 155 /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ 156 /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ 157 /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ 158 /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ 159 /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ 160 /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ 161 /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ 162 /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ 163 /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ 164 /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ 165 /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ 166 /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ 167 /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 168 /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ 169 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ 170 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ 171 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ 172 /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ 173 /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ 174 /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ 175 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 176 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 177 /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ 178 /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ 179 /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ 180 /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ 181 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 182 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 183 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 184 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 185 } 186}; 187 188/* ------------------------------------------------------------------------- */ 189 190/* 191 * Setup CS4 to enable the Board Control/Status registers. 192 * Otherwise the smcs won't work. 193*/ 194int board_early_init_f (void) 195{ 196 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; 197 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 198 volatile memctl8260_t *memctl = &immap->im_memctl; 199 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; 200 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; 201 regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ 202 regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ 203 return 0; 204} 205 206void 207reset_phy(void) 208{ 209 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; 210 regs->bcsr4 = 0xC3; 211} 212 213/* 214 * Check Board Identity: 215 */ 216 217int checkboard(void) 218{ 219 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; 220 printf ("Board: Embedded Planet RPX Super, Revision %d\n", 221 regs->bcsr0 >> 4); 222 223 return 0; 224} 225 226/* ------------------------------------------------------------------------- */ 227 228phys_size_t initdram(int board_type) 229{ 230 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 231 volatile memctl8260_t *memctl = &immap->im_memctl; 232 volatile uchar c = 0, *ramaddr; 233 ulong psdmr, lsdmr, bcr; 234 long size = 0; 235 int i; 236 237 psdmr = CONFIG_SYS_PSDMR; 238 lsdmr = CONFIG_SYS_LSDMR; 239 240 /* 241 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): 242 * 243 * "At system reset, initialization software must set up the 244 * programmable parameters in the memory controller banks registers 245 * (ORx, BRx, P/LSDMR). After all memory parameters are configured, 246 * system software should execute the following initialization sequence 247 * for each SDRAM device. 248 * 249 * 1. Issue a PRECHARGE-ALL-BANKS command 250 * 2. Issue eight CBR REFRESH commands 251 * 3. Issue a MODE-SET command to initialize the mode register 252 * 253 * The initial commands are executed by setting P/LSDMR[OP] and 254 * accessing the SDRAM with a single-byte transaction." 255 * 256 * The appropriate BRx/ORx registers have already been set when we 257 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. 258 */ 259 260 size = CONFIG_SYS_SDRAM0_SIZE; 261 bcr = immap->im_siu_conf.sc_bcr; 262 immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); 263 264 memctl->memc_mptpr = CONFIG_SYS_MPTPR; 265 266 ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE); 267 memctl->memc_psrt = CONFIG_SYS_PSRT; 268 269 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; 270 *ramaddr = c; 271 272 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; 273 for (i = 0; i < 8; i++) 274 *ramaddr = c; 275 276 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; 277 *ramaddr = c; 278 279 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; 280 *ramaddr = c; 281 282 immap->im_siu_conf.sc_bcr = bcr; 283 284#ifndef CONFIG_SYS_RAMBOOT 285/* size += CONFIG_SYS_SDRAM1_SIZE; */ 286 ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE); 287 memctl->memc_lsrt = CONFIG_SYS_LSRT; 288 289 memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; 290 *ramaddr = c; 291 292 memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; 293 for (i = 0; i < 8; i++) 294 *ramaddr = c; 295 296 memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; 297 *ramaddr = c; 298 299 memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; 300 *ramaddr = c; 301#endif 302 303 /* return total ram size */ 304 return (size * 1024 * 1024); 305} 306