LXR uboot/board/socrates/sdram.c

   1/*
   2 * (C) Copyright 2008
   3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24
  25#include <common.h>
  26#include <asm/processor.h>
  27#include <asm/immap_85xx.h>
  28#include <asm/fsl_ddr_sdram.h>
  29#include <asm/processor.h>
  30#include <asm/mmu.h>
  31#include <spd_sdram.h>
  32
  33
  34#if !defined(CONFIG_SPD_EEPROM)
  35/*
  36 * Autodetect onboard DDR SDRAM on 85xx platforms
  37 *
  38 * NOTE: Some of the hardcoded values are hardware dependant,
  39 *       so this should be extended for other future boards
  40 *       using this routine!
  41 */
  42phys_size_t fixed_sdram(void)
  43{
  44        volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
  45
  46        /*
  47         * Disable memory controller.
  48         */
  49        ddr->cs0_config = 0;
  50        ddr->sdram_cfg = 0;
  51
  52        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  53        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  54        ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  55        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  56        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  57        ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
  58        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  59        ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
  60        ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
  61
  62        asm ("sync;isync;msync");
  63        udelay(1000);
  64
  65        ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
  66        asm ("sync; isync; msync");
  67        udelay(1000);
  68
  69        if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
  70                /*
  71                 * OK, size detected -> all done
  72                 */
  73                return CONFIG_SYS_SDRAM_SIZE<<20;
  74        }
  75
  76        return 0;                               /* nothing found !              */
  77}
  78#endif
  79
  80#if defined(CONFIG_SYS_DRAM_TEST)
  81int testdram (void)
  82{
  83        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  84        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  85        uint *p;
  86
  87        printf ("SDRAM test phase 1:\n");
  88        for (p = pstart; p < pend; p++)
  89                *p = 0xaaaaaaaa;
  90
  91        for (p = pstart; p < pend; p++) {
  92                if (*p != 0xaaaaaaaa) {
  93                        printf ("SDRAM test fails at: %08x\n", (uint) p);
  94                        return 1;
  95                }
  96        }
  97
  98        printf ("SDRAM test phase 2:\n");
  99        for (p = pstart; p < pend; p++)
 100                *p = 0x55555555;
 101
 102        for (p = pstart; p < pend; p++) {
 103                if (*p != 0x55555555) {
 104                        printf ("SDRAM test fails at: %08x\n", (uint) p);
 105                        return 1;
 106                }
 107        }
 108
 109        printf ("SDRAM test passed.\n");
 110        return 0;
 111}
 112#endif
 113