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21#include <common.h>
22#include <asm/ppc440.h>
23#include <libfdt.h>
24#include <fdt_support.h>
25#include <i2c.h>
26#include <mtd/cfi_flash.h>
27#include <asm/processor.h>
28#include <asm/io.h>
29#include <asm/mmu.h>
30#include <asm/4xx_pcie.h>
31#include <asm/ppc4xx-gpio.h>
32
33int board_early_init_f(void)
34{
35
36
37
38 mtdcr(UIC0SR, 0xffffffff);
39 mtdcr(UIC0ER, 0x00000000);
40 mtdcr(UIC0CR, 0x00000005);
41 mtdcr(UIC0PR, 0xffffffff);
42 mtdcr(UIC0TR, 0x00000000);
43 mtdcr(UIC0VR, 0x00000000);
44 mtdcr(UIC0SR, 0xffffffff);
45
46 mtdcr(UIC1SR, 0xffffffff);
47 mtdcr(UIC1ER, 0x00000000);
48 mtdcr(UIC1CR, 0x00000000);
49 mtdcr(UIC1PR, 0x7fffffff);
50 mtdcr(UIC1TR, 0x00000000);
51 mtdcr(UIC1VR, 0x00000000);
52 mtdcr(UIC1SR, 0xffffffff);
53
54 mtdcr(UIC2SR, 0xffffffff);
55 mtdcr(UIC2ER, 0x00000000);
56 mtdcr(UIC2CR, 0x00000000);
57 mtdcr(UIC2PR, 0xffffffff);
58 mtdcr(UIC2TR, 0x00000000);
59 mtdcr(UIC2VR, 0x00000000);
60 mtdcr(UIC2SR, 0xffffffff);
61
62 mtdcr(UIC3SR, 0xffffffff);
63 mtdcr(UIC3ER, 0x00000000);
64 mtdcr(UIC3CR, 0x00000000);
65 mtdcr(UIC3PR, 0xffffffff);
66 mtdcr(UIC3TR, 0x00000000);
67 mtdcr(UIC3VR, 0x00000000);
68 mtdcr(UIC3SR, 0xffffffff);
69
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74
75 mtsdr(SDR0_PFC0, 0x00007fff);
76 mtsdr(SDR0_PFC1, 0x00040000);
77
78
79 mtsdr(SDR0_PCI0, 0xe0000000);
80
81 mtsdr(SDR0_SRST1, 0);
82
83
84 mtdcr(AHB_TOP, 0x8000004B);
85 mtdcr(AHB_BOT, 0x8000004B);
86
87 return 0;
88}
89
90int checkboard(void)
91{
92 char *s = getenv("serial#");
93
94 printf("Board: T3CORP");
95
96 if (s != NULL) {
97 puts(", serial# ");
98 puts(s);
99 }
100 putc('\n');
101
102 return 0;
103}
104
105int board_early_init_r(void)
106{
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117
118 mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
119 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
120
121
122 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
123
124
125 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
126 CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
127
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138 set_mcsr(get_mcsr());
139
140 return 0;
141}
142
143int misc_init_r(void)
144{
145 u32 sdr0_srst1 = 0;
146 u32 eth_cfg;
147
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151
152 mfsdr(SDR0_ETH_CFG, eth_cfg);
153
154 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
155 SDR0_ETH_CFG_SGMII1_ENABLE |
156 SDR0_ETH_CFG_SGMII0_ENABLE);
157
158
159 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
160 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
161 mtsdr(SDR0_ETH_CFG, eth_cfg);
162
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167 mfsdr(SDR0_SRST1, sdr0_srst1);
168 sdr0_srst1 &= ~SDR0_SRST1_AHB;
169 mtsdr(SDR0_SRST1, sdr0_srst1);
170
171 return 0;
172}
173
174int board_pcie_last(void)
175{
176
177
178
179 return 0;
180}
181
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185
186static struct sdram_timing board_scan_options[] = {
187 {1, 2},
188 {-1, -1}
189};
190
191struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
192{
193 return board_scan_options;
194}
195
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203
204u8 flash_read8(void *addr)
205{
206 u16 val = __raw_readw((void *)((u32)addr & ~1));
207
208 if ((u32)addr & 1)
209 return val;
210
211 return val >> 8;
212}
213
214u32 flash_read32(void *addr)
215{
216 return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
217}
218
219void flash_cmd_reset(flash_info_t *info)
220{
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225
226
227 if (info->start[0] == CONFIG_SYS_FLASH_BASE)
228 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
229 else
230 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
231}
232