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32#include <common.h>
33#include <command.h>
34#include <asm/processor.h>
35#include <asm/io.h>
36#include <pci.h>
37
38unsigned char ShortPCIListing = 1;
39
40
41
42
43
44void pci_header_show(pci_dev_t dev);
45void pci_header_show_brief(pci_dev_t dev);
46
47
48
49
50
51
52
53
54
55
56
57
58
59void pciinfo(int BusNum, int ShortPCIListing)
60{
61 int Device;
62 int Function;
63 unsigned char HeaderType;
64 unsigned short VendorID;
65 pci_dev_t dev;
66
67 printf("Scanning PCI devices on bus %d\n", BusNum);
68
69 if (ShortPCIListing) {
70 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
71 printf("_____________________________________________________________\n");
72 }
73
74 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
75 HeaderType = 0;
76 VendorID = 0;
77 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
78
79
80
81 if (Function && !(HeaderType & 0x80))
82 break;
83
84 dev = PCI_BDF(BusNum, Device, Function);
85
86 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
87 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
88 continue;
89
90 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
91
92 if (ShortPCIListing)
93 {
94 printf("%02x.%02x.%02x ", BusNum, Device, Function);
95 pci_header_show_brief(dev);
96 }
97 else
98 {
99 printf("\nFound PCI device %02x.%02x.%02x:\n",
100 BusNum, Device, Function);
101 pci_header_show(dev);
102 }
103 }
104 }
105}
106
107
108
109
110
111
112
113
114
115
116
117
118
119void pci_header_show_brief(pci_dev_t dev)
120{
121 u16 vendor, device;
122 u8 class, subclass;
123
124 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
125 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
126 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
127 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
128
129 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
130 vendor, device,
131 pci_class_str(class), subclass);
132}
133
134
135
136
137
138
139
140
141
142
143
144void pci_header_show(pci_dev_t dev)
145{
146 u8 _byte, header_type;
147 u16 _word;
148 u32 _dword;
149
150#define PRINT(msg, type, reg) \
151 pci_read_config_##type(dev, reg, &_##type); \
152 printf(msg, _##type)
153
154#define PRINT2(msg, type, reg, func) \
155 pci_read_config_##type(dev, reg, &_##type); \
156 printf(msg, _##type, func(_##type))
157
158 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
159
160 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
161 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
162 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
163 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
164 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
165 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
166 pci_class_str);
167 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
168 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
169 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
170 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
171 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
172 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
173 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
174
175 switch (header_type & 0x03) {
176 case PCI_HEADER_TYPE_NORMAL:
177 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
178 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
179 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
180 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
181 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
182 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
183 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
184 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
185 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
186 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
187 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
188 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
189 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
190 break;
191
192 case PCI_HEADER_TYPE_BRIDGE:
193
194 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
195 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
196 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
197 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
198 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
199 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
200 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
201 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
202 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
203 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
204 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
205 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
206 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
207 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
208 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
209 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
210 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
211 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
212 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
213 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
214 break;
215
216 case PCI_HEADER_TYPE_CARDBUS:
217
218 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
219 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
220 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
221 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
222 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
223 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
224 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
225 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
226 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
227 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
228 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
229 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
230 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
231 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
232 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
233 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
234 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
235 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
236 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
237 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
238 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
239 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
240 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
241 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
242 break;
243
244 default:
245 printf("unknown header\n");
246 break;
247 }
248
249#undef PRINT
250#undef PRINT2
251}
252
253
254
255static pci_dev_t get_pci_dev(char* name)
256{
257 char cnum[12];
258 int len, i, iold, n;
259 int bdfs[3] = {0,0,0};
260
261 len = strlen(name);
262 if (len > 8)
263 return -1;
264 for (i = 0, iold = 0, n = 0; i < len; i++) {
265 if (name[i] == '.') {
266 memcpy(cnum, &name[iold], i - iold);
267 cnum[i - iold] = '\0';
268 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
269 iold = i + 1;
270 }
271 }
272 strcpy(cnum, &name[iold]);
273 if (n == 0)
274 n = 1;
275 bdfs[n] = simple_strtoul(cnum, NULL, 16);
276 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
277}
278
279static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
280{
281#define DISP_LINE_LEN 16
282 ulong i, nbytes, linebytes;
283 int rc = 0;
284
285 if (length == 0)
286 length = 0x40 / size;
287
288
289
290
291 nbytes = length * size;
292 do {
293 uint val4;
294 ushort val2;
295 u_char val1;
296
297 printf("%08lx:", addr);
298 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
299 for (i=0; i<linebytes; i+= size) {
300 if (size == 4) {
301 pci_read_config_dword(bdf, addr, &val4);
302 printf(" %08x", val4);
303 } else if (size == 2) {
304 pci_read_config_word(bdf, addr, &val2);
305 printf(" %04x", val2);
306 } else {
307 pci_read_config_byte(bdf, addr, &val1);
308 printf(" %02x", val1);
309 }
310 addr += size;
311 }
312 printf("\n");
313 nbytes -= linebytes;
314 if (ctrlc()) {
315 rc = 1;
316 break;
317 }
318 } while (nbytes > 0);
319
320 return (rc);
321}
322
323static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
324{
325 if (size == 4) {
326 pci_write_config_dword(bdf, addr, value);
327 }
328 else if (size == 2) {
329 ushort val = value & 0xffff;
330 pci_write_config_word(bdf, addr, val);
331 }
332 else {
333 u_char val = value & 0xff;
334 pci_write_config_byte(bdf, addr, val);
335 }
336 return 0;
337}
338
339static int
340pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
341{
342 ulong i;
343 int nbytes;
344 extern char console_buffer[];
345 uint val4;
346 ushort val2;
347 u_char val1;
348
349
350
351
352 do {
353 printf("%08lx:", addr);
354 if (size == 4) {
355 pci_read_config_dword(bdf, addr, &val4);
356 printf(" %08x", val4);
357 }
358 else if (size == 2) {
359 pci_read_config_word(bdf, addr, &val2);
360 printf(" %04x", val2);
361 }
362 else {
363 pci_read_config_byte(bdf, addr, &val1);
364 printf(" %02x", val1);
365 }
366
367 nbytes = readline (" ? ");
368 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
369
370
371
372 if (incrflag)
373 addr += nbytes ? -size : size;
374 nbytes = 1;
375#ifdef CONFIG_BOOT_RETRY_TIME
376 reset_cmd_timeout();
377#endif
378 }
379#ifdef CONFIG_BOOT_RETRY_TIME
380 else if (nbytes == -2) {
381 break;
382 }
383#endif
384 else {
385 char *endp;
386 i = simple_strtoul(console_buffer, &endp, 16);
387 nbytes = endp - console_buffer;
388 if (nbytes) {
389#ifdef CONFIG_BOOT_RETRY_TIME
390
391
392 reset_cmd_timeout();
393#endif
394 pci_cfg_write (bdf, addr, size, i);
395 if (incrflag)
396 addr += size;
397 }
398 }
399 } while (nbytes);
400
401 return 0;
402}
403
404
405
406
407
408
409
410
411
412int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
413{
414 ulong addr = 0, value = 0, size = 0;
415 pci_dev_t bdf = 0;
416 char cmd = 's';
417
418 if (argc > 1)
419 cmd = argv[1][0];
420
421 switch (cmd) {
422 case 'd':
423 case 'n':
424 case 'm':
425 case 'w':
426
427 size = cmd_get_data_size(argv[1], 4);
428 if (argc > 3)
429 addr = simple_strtoul(argv[3], NULL, 16);
430 if (argc > 4)
431 value = simple_strtoul(argv[4], NULL, 16);
432 case 'h':
433 if (argc < 3)
434 goto usage;
435 if ((bdf = get_pci_dev(argv[2])) == -1)
436 return 1;
437 break;
438#ifdef CONFIG_CMD_PCI_ENUM
439 case 'e':
440 break;
441#endif
442 default:
443 value = 1;
444 bdf = 0;
445 if (argc > 1) {
446 if (argv[argc-1][0] == 'l') {
447 value = 0;
448 argc--;
449 }
450 if (argc > 1)
451 bdf = simple_strtoul(argv[1], NULL, 16);
452 }
453 pciinfo(bdf, value);
454 return 0;
455 }
456
457 switch (argv[1][0]) {
458 case 'h':
459 pci_header_show(bdf);
460 return 0;
461 case 'd':
462 return pci_cfg_display(bdf, addr, size, value);
463#ifdef CONFIG_CMD_PCI_ENUM
464 case 'e':
465 pci_init();
466 return 0;
467#endif
468 case 'n':
469 if (argc < 4)
470 goto usage;
471 return pci_cfg_modify(bdf, addr, size, value, 0);
472 case 'm':
473 if (argc < 4)
474 goto usage;
475 return pci_cfg_modify(bdf, addr, size, value, 1);
476 case 'w':
477 if (argc < 5)
478 goto usage;
479 return pci_cfg_write(bdf, addr, size, value);
480 }
481
482 return 1;
483 usage:
484 return cmd_usage(cmdtp);
485}
486
487
488
489
490U_BOOT_CMD(
491 pci, 5, 1, do_pci,
492 "list and access PCI Configuration Space",
493 "[bus] [long]\n"
494 " - short or long list of PCI devices on bus 'bus'\n"
495#ifdef CONFIG_CMD_PCI_ENUM
496 "pci enum\n"
497 " - re-enumerate PCI buses\n"
498#endif
499 "pci header b.d.f\n"
500 " - show header of PCI device 'bus.device.function'\n"
501 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
502 " - display PCI configuration space (CFG)\n"
503 "pci next[.b, .w, .l] b.d.f address\n"
504 " - modify, read and keep CFG address\n"
505 "pci modify[.b, .w, .l] b.d.f address\n"
506 " - modify, auto increment CFG address\n"
507 "pci write[.b, .w, .l] b.d.f address value\n"
508 " - write to CFG address"
509);
510
