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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36#define CONFIG_405EP 1
37#define CONFIG_4xx 1
38#define CONFIG_HUB405 1
39
40#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
41
42#define CONFIG_BOARD_EARLY_INIT_F 1
43#define CONFIG_MISC_INIT_R 1
44
45#define CONFIG_SYS_CLK_FREQ 33330000
46
47#define CONFIG_BOARD_TYPES 1
48
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_BOOTDELAY 3
51
52#undef CONFIG_BOOTARGS
53#undef CONFIG_BOOTCOMMAND
54
55#define CONFIG_PREBOOT
56
57#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
58
59#define CONFIG_PPC4xx_EMAC
60#define CONFIG_MII 1
61#define CONFIG_PHY_ADDR 0
62#define CONFIG_LXT971_NO_SLEEP 1
63
64#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
65#define CONFIG_NET_MULTI
66
67
68
69
70
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
77
78
79
80#include <config_cmd_default.h>
81
82#define CONFIG_CMD_DHCP
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_ELF
85#define CONFIG_CMD_NAND
86#define CONFIG_CMD_I2C
87#define CONFIG_CMD_MII
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_EEPROM
90
91
92#undef CONFIG_WATCHDOG
93
94#define CONFIG_SDRAM_BANK0 1
95
96
97
98
99#define CONFIG_SYS_LONGHELP
100#define CONFIG_SYS_PROMPT "=> "
101
102#undef CONFIG_SYS_HUSH_PARSER
103#ifdef CONFIG_SYS_HUSH_PARSER
104#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
105#endif
106
107#if defined(CONFIG_CMD_KGDB)
108#define CONFIG_SYS_CBSIZE 1024
109#else
110#define CONFIG_SYS_CBSIZE 256
111#endif
112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
113#define CONFIG_SYS_MAXARGS 16
114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
115
116#define CONFIG_SYS_DEVICE_NULLDEV 1
117
118#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
119
120#define CONFIG_SYS_MEMTEST_START 0x0400000
121#define CONFIG_SYS_MEMTEST_END 0x0C00000
122
123#define CONFIG_CONS_INDEX 1
124#define CONFIG_SYS_NS16550
125#define CONFIG_SYS_NS16550_SERIAL
126#define CONFIG_SYS_NS16550_REG_SIZE 1
127#define CONFIG_SYS_NS16550_CLK get_serial_clock()
128
129#undef CONFIG_SYS_EXT_SERIAL_CLOCK
130#define CONFIG_SYS_BASE_BAUD 691200
131
132
133#define CONFIG_SYS_BAUDRATE_TABLE \
134 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
135 57600, 115200, 230400, 460800, 921600 }
136
137#define CONFIG_SYS_LOAD_ADDR 0x100000
138#define CONFIG_SYS_EXTBDINFO 1
139
140#define CONFIG_SYS_HZ 1000
141
142#define CONFIG_ZERO_BOOTDELAY_CHECK
143
144#define CONFIG_VERSION_VARIABLE 1
145
146#define CONFIG_SYS_RX_ETH_BUFFER 16
147
148
149#define CONFIG_ENV_OVERWRITE
150#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
151#define CONFIG_HAS_ETH1
152#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
153
154
155
156
157
158#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
159#define CONFIG_SYS_MAX_NAND_DEVICE 1
160#define NAND_BIG_DELAY_US 25
161
162#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
163#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
164#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
165#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
166
167#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
168#define CONFIG_SYS_NAND_QUIET 1
169
170
171
172
173
174#define PCI_HOST_ADAPTER 0
175#define PCI_HOST_FORCE 1
176#define PCI_HOST_AUTO 2
177
178#undef CONFIG_PCI
179#define CONFIG_PCI_HOST PCI_HOST_HOST
180#undef CONFIG_PCI_PNP
181
182
183#undef CONFIG_PCI_SCAN_SHOW
184
185#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
186#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
187#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
188#define CONFIG_SYS_PCI_PTM1LA 0x00000000
189#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
190#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
191#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
192#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
193#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
194
195
196
197
198
199
200#define CONFIG_SYS_SDRAM_BASE 0x00000000
201#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
202#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
203#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
204#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
205
206
207
208
209
210
211#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
212
213
214
215#define CONFIG_SYS_MAX_FLASH_BANKS 1
216#define CONFIG_SYS_MAX_FLASH_SECT 256
217
218#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
219#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
220
221#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
222#define CONFIG_SYS_FLASH_ADDR0 0x5555
223#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
224
225
226
227
228#define CONFIG_SYS_FLASH_READ0 0x0000
229#define CONFIG_SYS_FLASH_READ1 0x0001
230#define CONFIG_SYS_FLASH_READ2 0x0002
231
232#define CONFIG_SYS_FLASH_EMPTY_INFO
233
234#if 0
235#define CONFIG_SYS_JFFS2_FIRST_BANK 0
236#define CONFIG_SYS_JFFS2_NUM_BANKS 1
237#endif
238
239
240
241
242#define CONFIG_ENV_IS_IN_EEPROM 1
243#define CONFIG_ENV_OFFSET 0x100
244#define CONFIG_ENV_SIZE 0x700
245
246
247#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
248#define CONFIG_SYS_NVRAM_SIZE 242
249
250
251
252
253#define CONFIG_HARD_I2C
254#define CONFIG_PPC4XX_I2C
255#define CONFIG_SYS_I2C_SPEED 400000
256#define CONFIG_SYS_I2C_SLAVE 0x7F
257
258#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
259#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
260
261#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
262#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
263
264
265#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
266
267
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270
271
272
273#define FLASH_BASE0_PRELIM 0xFFC00000
274
275
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278
279
280#define CONFIG_SYS_EBC_PB0AP 0x92015480
281
282#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
283
284
285#define CONFIG_SYS_EBC_PB1AP 0x92015480
286#define CONFIG_SYS_EBC_PB1CR 0xF4018000
287
288
289#if 0
290#define CONFIG_SYS_EBC_PB2AP 0x010053C0
291#define CONFIG_SYS_EBC_PB2CR 0xF0018000
292#else
293#define CONFIG_SYS_EBC_PB2AP 0x92015480
294#define CONFIG_SYS_EBC_PB2CR 0xF0018000
295#endif
296
297#define DUART0_BA 0xF0000000
298#define DUART1_BA 0xF0000008
299#define DUART2_BA 0xF0000010
300#define DUART3_BA 0xF0000018
301#define CONFIG_SYS_NAND_BASE 0xF4000000
302
303
304
305
306#define CONFIG_SYS_FPGA_SPARTAN2 1
307#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
308
309
310#define CONFIG_SYS_FPGA_PRG 0x04000000
311#define CONFIG_SYS_FPGA_CLK 0x02000000
312#define CONFIG_SYS_FPGA_DATA 0x01000000
313#define CONFIG_SYS_FPGA_INIT 0x00010000
314#define CONFIG_SYS_FPGA_DONE 0x00008000
315
316
317
318
319
320#define CONFIG_SYS_TEMP_STACK_OCM 1
321
322
323#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
324#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
325#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
326#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
327
328#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
329#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
330
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340
341
342
343#define CONFIG_SYS_GPIO0_OSRL 0x40000550
344#define CONFIG_SYS_GPIO0_OSRH 0x00000110
345#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
346#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
347#define CONFIG_SYS_GPIO0_TSRL 0x00000000
348#define CONFIG_SYS_GPIO0_TSRH 0x00000000
349#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
350
351#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
352#define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5)
353#define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6)
354#define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7)
355#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8)
356
357
358
359
360
361#if 0
362#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
363#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
364#endif
365#if 0
366#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
367#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
368#endif
369#if 1
370#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
371#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
372#endif
373
374#endif
375