1/* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M5475EVB_H 31#define _M5475EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF547x_8x /* define processor family */ 38#define CONFIG_M547x /* define processor type */ 39#define CONFIG_M5475 /* define processor type */ 40 41#define CONFIG_MCFUART 42#define CONFIG_SYS_UART_PORT (0) 43#define CONFIG_BAUDRATE 115200 44#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46#define CONFIG_HW_WATCHDOG 47#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 48 49/* Command line configuration */ 50#include <config_cmd_default.h> 51 52#define CONFIG_CMD_CACHE 53#undef CONFIG_CMD_DATE 54#define CONFIG_CMD_ELF 55#define CONFIG_CMD_FLASH 56#define CONFIG_CMD_I2C 57#define CONFIG_CMD_MEMORY 58#define CONFIG_CMD_MISC 59#define CONFIG_CMD_MII 60#define CONFIG_CMD_NET 61#define CONFIG_CMD_PCI 62#define CONFIG_CMD_PING 63#define CONFIG_CMD_REGINFO 64#define CONFIG_CMD_USB 65 66#define CONFIG_SLTTMR 67 68#define CONFIG_FSLDMAFEC 69#ifdef CONFIG_FSLDMAFEC 70# define CONFIG_NET_MULTI 1 71# define CONFIG_MII 1 72# define CONFIG_MII_INIT 1 73# define CONFIG_HAS_ETH1 74 75# define CONFIG_SYS_DMA_USE_INTSRAM 1 76# define CONFIG_SYS_DISCOVER_PHY 77# define CONFIG_SYS_RX_ETH_BUFFER 32 78# define CONFIG_SYS_TX_ETH_BUFFER 48 79# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 80 81# define CONFIG_SYS_FEC0_PINMUX 0 82# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 83# define CONFIG_SYS_FEC1_PINMUX 0 84# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 85 86# define MCFFEC_TOUT_LOOP 50000 87/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 88# ifndef CONFIG_SYS_DISCOVER_PHY 89# define FECDUPLEX FULL 90# define FECSPEED _100BASET 91# else 92# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 93# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 94# endif 95# endif /* CONFIG_SYS_DISCOVER_PHY */ 96 97# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 98# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 99# define CONFIG_IPADDR 192.162.1.2 100# define CONFIG_NETMASK 255.255.255.0 101# define CONFIG_SERVERIP 192.162.1.1 102# define CONFIG_GATEWAYIP 192.162.1.1 103# define CONFIG_OVERWRITE_ETHADDR_ONCE 104 105#endif 106 107#ifdef CONFIG_CMD_USB 108# define CONFIG_USB_OHCI_NEW 109# define CONFIG_USB_STORAGE 110 111# ifndef CONFIG_CMD_PCI 112# define CONFIG_CMD_PCI 113# endif 114# define CONFIG_PCI_OHCI 115# define CONFIG_DOS_PARTITION 116 117# undef CONFIG_SYS_USB_OHCI_BOARD_INIT 118# undef CONFIG_SYS_USB_OHCI_CPU_INIT 119# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 120# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 121# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 122#endif 123 124/* I2C */ 125#define CONFIG_FSL_I2C 126#define CONFIG_HARD_I2C /* I2C with hw support */ 127#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 128#define CONFIG_SYS_I2C_SPEED 80000 129#define CONFIG_SYS_I2C_SLAVE 0x7F 130#define CONFIG_SYS_I2C_OFFSET 0x00008F00 131#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 132 133/* PCI */ 134#ifdef CONFIG_CMD_PCI 135#define CONFIG_PCI 1 136#define CONFIG_PCI_PNP 1 137#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 138 139#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 140 141#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 142#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 143#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 144 145#define CONFIG_SYS_PCI_IO_BUS 0x71000000 146#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 147#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 148 149#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 150#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 151#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 152#endif 153 154#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 155#define CONFIG_UDP_CHECKSUM 156 157#ifdef CONFIG_MCFFEC 158# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 159# define CONFIG_IPADDR 192.162.1.2 160# define CONFIG_NETMASK 255.255.255.0 161# define CONFIG_SERVERIP 192.162.1.1 162# define CONFIG_GATEWAYIP 192.162.1.1 163# define CONFIG_OVERWRITE_ETHADDR_ONCE 164#endif /* FEC_ENET */ 165 166#define CONFIG_HOSTNAME M547xEVB 167#define CONFIG_EXTRA_ENV_SETTINGS \ 168 "netdev=eth0\0" \ 169 "loadaddr=10000\0" \ 170 "u-boot=u-boot.bin\0" \ 171 "load=tftp ${loadaddr) ${u-boot}\0" \ 172 "upd=run load; run prog\0" \ 173 "prog=prot off bank 1;" \ 174 "era ff800000 ff82ffff;" \ 175 "cp.b ${loadaddr} ff800000 ${filesize};"\ 176 "save\0" \ 177 "" 178 179#define CONFIG_PRAM 512 /* 512 KB */ 180#define CONFIG_SYS_PROMPT "-> " 181#define CONFIG_SYS_LONGHELP /* undef to save memory */ 182 183#ifdef CONFIG_CMD_KGDB 184# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 185#else 186# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 187#endif 188 189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 190#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 191#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 192#define CONFIG_SYS_LOAD_ADDR 0x00010000 193 194#define CONFIG_SYS_HZ 1000 195#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 196#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 197 198#define CONFIG_SYS_MBAR 0xF0000000 199#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 200#define CONFIG_SYS_INTSRAMSZ 0x8000 201 202/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 203 204/* 205 * Low Level Configuration Settings 206 * (address mappings, register initial values, etc.) 207 * You should know what you are doing if you make changes here. 208 */ 209/*----------------------------------------------------------------------- 210 * Definitions for initial stack pointer and data area (in DPRAM) 211 */ 212#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 213#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 214#define CONFIG_SYS_INIT_RAM_CTRL 0x21 215#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 216#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 217#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 218#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 221/*----------------------------------------------------------------------- 222 * Start addresses for the final memory configuration 223 * (Set up by the startup code) 224 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 225 */ 226#define CONFIG_SYS_SDRAM_BASE 0x00000000 227#define CONFIG_SYS_SDRAM_CFG1 0x73711630 228#define CONFIG_SYS_SDRAM_CFG2 0x46770000 229#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 230#define CONFIG_SYS_SDRAM_EMOD 0x40010000 231#define CONFIG_SYS_SDRAM_MODE 0x018D0000 232#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 233#ifdef CONFIG_SYS_DRAMSZ1 234# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 235#else 236# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 237#endif 238 239#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 240#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 241 242#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 243#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 244 245#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 246#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 247 248/* 249 * For booting Linux, the board info and command line data 250 * have to be in the first 8 MB of memory, since this is 251 * the maximum mapped by the Linux kernel during initialization ?? 252 */ 253#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 254 255/*----------------------------------------------------------------------- 256 * FLASH organization 257 */ 258#define CONFIG_SYS_FLASH_CFI 259#ifdef CONFIG_SYS_FLASH_CFI 260# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 261# define CONFIG_FLASH_CFI_DRIVER 1 262# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 263# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 264# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 265# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 266#ifdef CONFIG_SYS_NOR1SZ 267# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 268# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 269# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 270#else 271# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 272# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 273#endif 274#endif 275 276/* Configuration for environment 277 * Environment is embedded in u-boot in the second sector of the flash 278 */ 279#define CONFIG_ENV_OFFSET 0x2000 280#define CONFIG_ENV_SECT_SIZE 0x2000 281#define CONFIG_ENV_IS_IN_FLASH 1 282 283/*----------------------------------------------------------------------- 284 * Cache Configuration 285 */ 286#define CONFIG_SYS_CACHELINE_SIZE 16 287 288#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 289 CONFIG_SYS_INIT_RAM_SIZE - 8) 290#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 291 CONFIG_SYS_INIT_RAM_SIZE - 4) 292#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 293 CF_CACR_IDCM) 294#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 295#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 296 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 297 CF_ACR_EN | CF_ACR_SM_ALL) 298#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 299 CF_CACR_IEC | CF_CACR_ICINVA) 300#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 301 CF_CACR_DEC | CF_CACR_DDCM_P | \ 302 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 303 304/*----------------------------------------------------------------------- 305 * Chipselect bank definitions 306 */ 307/* 308 * CS0 - NOR Flash 1, 2, 4, or 8MB 309 * CS1 - NOR Flash 310 * CS2 - Available 311 * CS3 - Available 312 * CS4 - Available 313 * CS5 - Available 314 */ 315#define CONFIG_SYS_CS0_BASE 0xFF800000 316#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 317#define CONFIG_SYS_CS0_CTRL 0x00101980 318 319#ifdef CONFIG_SYS_NOR1SZ 320#define CONFIG_SYS_CS1_BASE 0xE0000000 321#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 322#define CONFIG_SYS_CS1_CTRL 0x00101D80 323#endif 324 325#endif /* _M5475EVB_H */ 326