1/* 2 * (C) Copyright 2000-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr 26 * U-Boot port on NetTA4 board 27 */ 28 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 33#error Unsupported CONFIG_NETPHONE version 34#endif 35 36/* 37 * High Level Configuration Options 38 * (easy to change) 39 */ 40 41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ 42#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ 43 44#define CONFIG_SYS_TEXT_BASE 0x40000000 45 46#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 47#undef CONFIG_8xx_CONS_SMC2 48#undef CONFIG_8xx_CONS_NONE 49 50#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 51 52/* #define CONFIG_XIN 10000000 */ 53#define CONFIG_XIN 50000000 54/* #define MPC8XX_HZ 120000000 */ 55#define MPC8XX_HZ 66666666 56 57#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ 58 59#if 0 60#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 61#else 62#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 63#endif 64 65#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ 66 67#define CONFIG_PREBOOT "echo;" 68 69#undef CONFIG_BOOTARGS 70#define CONFIG_BOOTCOMMAND \ 71 "tftpboot; " \ 72 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 74 "bootm" 75 76#define CONFIG_SOURCE 77#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 78#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 79 80#undef CONFIG_WATCHDOG /* watchdog disabled */ 81 82#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 83 84#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 85#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ 86 87/* 88 * BOOTP options 89 */ 90#define CONFIG_BOOTP_SUBNETMASK 91#define CONFIG_BOOTP_GATEWAY 92#define CONFIG_BOOTP_HOSTNAME 93#define CONFIG_BOOTP_BOOTPATH 94#define CONFIG_BOOTP_BOOTFILESIZE 95#define CONFIG_BOOTP_NISDOMAIN 96 97#undef CONFIG_MAC_PARTITION 98#undef CONFIG_DOS_PARTITION 99 100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 101 102#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ 103#define FEC_ENET 1 /* eth.c needs it that way... */ 104#undef CONFIG_SYS_DISCOVER_PHY 105#define CONFIG_MII 1 106#define CONFIG_MII_INIT 1 107#define CONFIG_RMII 1 /* use RMII interface */ 108 109#define CONFIG_ETHER_ON_FEC1 1 110#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ 111#define CONFIG_FEC1_PHY_NORXERR 1 112 113#define CONFIG_ETHER_ON_FEC2 1 114#define CONFIG_FEC2_PHY 4 115#define CONFIG_FEC2_PHY_NORXERR 1 116 117#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ 118 119 120/* 121 * Command line configuration. 122 */ 123#include <config_cmd_default.h> 124 125#define CONFIG_CMD_DHCP 126#define CONFIG_CMD_PING 127#define CONFIG_CMD_MII 128#define CONFIG_CMD_CDP 129 130 131#define CONFIG_BOARD_EARLY_INIT_F 1 132#define CONFIG_MISC_INIT_R 133 134/* 135 * Miscellaneous configurable options 136 */ 137#define CONFIG_SYS_LONGHELP /* undef to save memory */ 138#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 139 140#define CONFIG_SYS_HUSH_PARSER 1 141#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 142 143#if defined(CONFIG_CMD_KGDB) 144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 145#else 146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 147#endif 148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 151 152#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ 153#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ 154 155#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 156 157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 158 159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 160 161/* 162 * Low Level Configuration Settings 163 * (address mappings, register initial values, etc.) 164 * You should know what you are doing if you make changes here. 165 */ 166/*----------------------------------------------------------------------- 167 * Internal Memory Mapped Register 168 */ 169#define CONFIG_SYS_IMMR 0xFF000000 170 171/*----------------------------------------------------------------------- 172 * Definitions for initial stack pointer and data area (in DPRAM) 173 */ 174#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 175#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ 176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178 179/*----------------------------------------------------------------------- 180 * Start addresses for the final memory configuration 181 * (Set up by the startup code) 182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 183 */ 184#define CONFIG_SYS_SDRAM_BASE 0x00000000 185#define CONFIG_SYS_FLASH_BASE 0x40000000 186#if defined(DEBUG) 187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188#else 189#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 190#endif 191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 192#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 193#if CONFIG_NETPHONE_VERSION == 2 194#define CONFIG_SYS_FLASH_BASE4 0x40080000 195#endif 196 197#define CONFIG_SYS_RESET_ADDRESS 0x80000000 198 199/* 200 * For booting Linux, the board info and command line data 201 * have to be in the first 8 MB of memory, since this is 202 * the maximum mapped by the Linux kernel during initialization. 203 */ 204#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 205 206/*----------------------------------------------------------------------- 207 * FLASH organization 208 */ 209#if CONFIG_NETPHONE_VERSION == 1 210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 211#elif CONFIG_NETPHONE_VERSION == 2 212#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 213#endif 214#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 215 216#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 217#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 218 219#define CONFIG_ENV_IS_IN_FLASH 1 220#define CONFIG_ENV_SECT_SIZE 0x10000 221 222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) 223#define CONFIG_ENV_SIZE 0x4000 224 225#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) 226#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 227 228/*----------------------------------------------------------------------- 229 * Cache Configuration 230 */ 231#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 232#if defined(CONFIG_CMD_KGDB) 233#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 234#endif 235 236/*----------------------------------------------------------------------- 237 * SYPCR - System Protection Control 11-9 238 * SYPCR can only be written once after reset! 239 *----------------------------------------------------------------------- 240 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 241 */ 242#if defined(CONFIG_WATCHDOG) 243#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 244 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 245#else 246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 247#endif 248 249/*----------------------------------------------------------------------- 250 * SIUMCR - SIU Module Configuration 11-6 251 *----------------------------------------------------------------------- 252 * PCMCIA config., multi-function pin tri-state 253 */ 254#ifndef CONFIG_CAN_DRIVER 255#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 256#else /* we must activate GPL5 in the SIUMCR for CAN */ 257#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 258#endif /* CONFIG_CAN_DRIVER */ 259 260/*----------------------------------------------------------------------- 261 * TBSCR - Time Base Status and Control 11-26 262 *----------------------------------------------------------------------- 263 * Clear Reference Interrupt Status, Timebase freezing enabled 264 */ 265#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 266 267/*----------------------------------------------------------------------- 268 * RTCSC - Real-Time Clock Status and Control Register 11-27 269 *----------------------------------------------------------------------- 270 */ 271#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 272 273/*----------------------------------------------------------------------- 274 * PISCR - Periodic Interrupt Status and Control 11-31 275 *----------------------------------------------------------------------- 276 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 277 */ 278#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 279 280/*----------------------------------------------------------------------- 281 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 282 *----------------------------------------------------------------------- 283 * Reset PLL lock status sticky bit, timer expired status bit and timer 284 * interrupt status bit 285 * 286 */ 287 288#if CONFIG_XIN == 10000000 289 290#if MPC8XX_HZ == 120000000 291#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 292 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 293 PLPRCR_TEXPS) 294#elif MPC8XX_HZ == 100000000 295#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 296 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 297 PLPRCR_TEXPS) 298#elif MPC8XX_HZ == 50000000 299#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 300 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 301 PLPRCR_TEXPS) 302#elif MPC8XX_HZ == 25000000 303#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 304 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 305 PLPRCR_TEXPS) 306#elif MPC8XX_HZ == 40000000 307#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 308 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 309 PLPRCR_TEXPS) 310#elif MPC8XX_HZ == 75000000 311#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 312 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 313 PLPRCR_TEXPS) 314#else 315#error unsupported CPU freq for XIN = 10MHz 316#endif 317 318#elif CONFIG_XIN == 50000000 319 320#if MPC8XX_HZ == 120000000 321#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 322 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 323 PLPRCR_TEXPS) 324#elif MPC8XX_HZ == 100000000 325#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 326 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 327 PLPRCR_TEXPS) 328#elif MPC8XX_HZ == 66666666 329#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 330 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 331 PLPRCR_TEXPS) 332#else 333#error unsupported CPU freq for XIN = 50MHz 334#endif 335 336#else 337 338#error unsupported XIN freq 339#endif 340 341 342/* 343 *----------------------------------------------------------------------- 344 * SCCR - System Clock and reset Control Register 15-27 345 *----------------------------------------------------------------------- 346 * Set clock output, timebase and RTC source and divider, 347 * power management and some other internal clocks 348 * 349 * Note: When TBS == 0 the timebase is independent of current cpu clock. 350 */ 351 352#define SCCR_MASK SCCR_EBDF11 353#if MPC8XX_HZ > 66666666 354#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 355 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 356 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 357 SCCR_DFALCD00 | SCCR_EBDF01) 358#else 359#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 360 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 361 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 362 SCCR_DFALCD00) 363#endif 364 365/*----------------------------------------------------------------------- 366 * 367 *----------------------------------------------------------------------- 368 * 369 */ 370/*#define CONFIG_SYS_DER 0x2002000F*/ 371#define CONFIG_SYS_DER 0 372 373/* 374 * Init Memory Controller: 375 * 376 * BR0/1 and OR0/1 (FLASH) 377 */ 378 379#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 380 381/* used to re-map FLASH both when starting from SRAM or FLASH: 382 * restrict access enough to keep SRAM working (if any) 383 * but not too much to meddle with FLASH accesses 384 */ 385#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 386#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 387 388/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 389#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) 390 391#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 392#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 393#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 394 395#if CONFIG_NETPHONE_VERSION == 2 396 397#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ 398 399#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 400#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 401#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 402 403#endif 404 405/* 406 * BR3 and OR3 (SDRAM) 407 * 408 */ 409#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ 410#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ 411 412/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 413#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) 414 415#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) 416#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) 417 418/* 419 * Memory Periodic Timer Prescaler 420 */ 421 422/* 423 * Memory Periodic Timer Prescaler 424 * 425 * The Divider for PTA (refresh timer) configuration is based on an 426 * example SDRAM configuration (64 MBit, one bank). The adjustment to 427 * the number of chip selects (NCS) and the actually needed refresh 428 * rate is done by setting MPTPR. 429 * 430 * PTA is calculated from 431 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 432 * 433 * gclk CPU clock (not bus clock!) 434 * Trefresh Refresh cycle * 4 (four word bursts used) 435 * 436 * 4096 Rows from SDRAM example configuration 437 * 1000 factor s -> ms 438 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 439 * 4 Number of refresh cycles per period 440 * 64 Refresh cycle in ms per number of rows 441 * -------------------------------------------- 442 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 443 * 444 * 50 MHz => 50.000.000 / Divider = 98 445 * 66 Mhz => 66.000.000 / Divider = 129 446 * 80 Mhz => 80.000.000 / Divider = 156 447 */ 448 449#define CONFIG_SYS_MAMR_PTA 234 450 451/* 452 * For 16 MBit, refresh rates could be 31.3 us 453 * (= 64 ms / 2K = 125 / quad bursts). 454 * For a simpler initialization, 15.6 us is used instead. 455 * 456 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 457 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 458 */ 459#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 460#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 461 462/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 463#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 464#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 465 466/* 467 * MAMR settings for SDRAM 468 */ 469 470/* 8 column SDRAM */ 471#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 474 475/* 9 column SDRAM */ 476#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 477 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 479 480#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ 481 482/****************************************************************/ 483 484#define DSP_SIZE 0x00010000 /* 64K */ 485#define NAND_SIZE 0x00010000 /* 64K */ 486 487#define DSP_BASE 0xF1000000 488#define NAND_BASE 0xF1010000 489 490/*****************************************************************************/ 491 492#define CONFIG_SYS_DIRECT_FLASH_TFTP 493 494/*****************************************************************************/ 495 496#if CONFIG_NETPHONE_VERSION == 1 497#define STATUS_LED_BIT 0x00000008 /* bit 28 */ 498#elif CONFIG_NETPHONE_VERSION == 2 499#define STATUS_LED_BIT 0x00000080 /* bit 24 */ 500#endif 501 502#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 503#define STATUS_LED_STATE STATUS_LED_BLINKING 504 505#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ 506#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ 507 508#ifndef __ASSEMBLY__ 509 510/* LEDs */ 511 512/* led_id_t is unsigned int mask */ 513typedef unsigned int led_id_t; 514 515#define __led_toggle(_msk) \ 516 do { \ 517 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ 518 } while(0) 519 520#define __led_set(_msk, _st) \ 521 do { \ 522 if ((_st)) \ 523 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ 524 else \ 525 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ 526 } while(0) 527 528#define __led_init(msk, st) __led_set(msk, st) 529 530#endif 531 532/*********************************************************************************************************** 533 534 ---------------------------------------------------------------------------------------------- 535 536 (V1) version 1 of the board 537 (V2) version 2 of the board 538 539 ---------------------------------------------------------------------------------------------- 540 541 Pin definitions: 542 543 +------+----------------+--------+------------------------------------------------------------ 544 | # | Name | Type | Comment 545 +------+----------------+--------+------------------------------------------------------------ 546 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select 547 | PA7 | DSP_INT | Output | DSP interrupt 548 | PA10 | DSP_RESET | Output | DSP reset 549 | PA14 | USBOE | Output | USB (1) 550 | PA15 | USBRXD | Output | USB (1) 551 | PB19 | BT_RTS | Output | Bluetooth (0) 552 | PB23 | BT_CTS | Output | Bluetooth (0) 553 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select 554 | PB27 | SPICS_DISP | Output | Display chip select 555 | PB28 | SPI_RXD_3V | Input | SPI Data Rx 556 | PB29 | SPI_TXD | Output | SPI Data Tx 557 | PB30 | SPI_CLK | Output | SPI Clock 558 | PC10 | DISPA0 | Output | Display A0 559 | PC11 | BACKLIGHT | Output | Display backlit 560 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD 561 | | IO_RESET | Output | (V2) General I/O reset 562 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) 563 | | HOOK | Input | (V2) Hook input interrupt 564 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK 565 | | F_RY_BY | Input | (V2) NAND F_RY_BY 566 | PE17 | F_ALE | Output | NAND F_ALE 567 | PE18 | F_CLE | Output | NAND F_CLE 568 | PE20 | F_CE | Output | NAND F_CE 569 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select 570 | | LED | Output | (V2) LED 571 | PE27 | SPICS_ER | Output | External serial register CS 572 | PE28 | LEDIO1 | Output | (V1) LED 573 | | BKBR1 | Input | (V2) Keyboard input scan 574 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) 575 | | BKBR2 | Input | (V2) Keyboard input scan 576 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) 577 | | BKBR3 | Input | (V2) Keyboard input scan 578 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY 579 | | BKBR4 | Input | (V2) Keyboard input scan 580 +------+----------------+--------+--------------------------------------------------- 581 582 ---------------------------------------------------------------------------------------------- 583 584 Serial register input: 585 586 +------+----------------+------------------------------------------------------------ 587 | # | Name | Comment 588 +------+----------------+------------------------------------------------------------ 589 | 0 | BKBR1 | (V1) Keyboard input scan 590 | 1 | BKBR3 | (V1) Keyboard input scan 591 | 2 | BKBR4 | (V1) Keyboard input scan 592 | 3 | BKBR2 | (V1) Keyboard input scan 593 | 4 | HOOK | (V1) Hook switch 594 | 5 | BT_LINK | (V1) Bluetooth link status 595 | 6 | HOST_WAKE | (V1) Bluetooth host wake up 596 | 7 | OK_ETH | (V1) Cisco inline power OK status 597 +------+----------------+------------------------------------------------------------ 598 599 ---------------------------------------------------------------------------------------------- 600 601 Serial register output: 602 603 +------+----------------+------------------------------------------------------------ 604 | # | Name | Comment 605 +------+----------------+------------------------------------------------------------ 606 | 0 | KEY1 | Keyboard output scan 607 | 1 | KEY2 | Keyboard output scan 608 | 2 | KEY3 | Keyboard output scan 609 | 3 | KEY4 | Keyboard output scan 610 | 4 | KEY5 | Keyboard output scan 611 | 5 | KEY6 | Keyboard output scan 612 | 6 | KEY7 | Keyboard output scan 613 | 7 | BT_WAKE | Bluetooth wake up 614 +------+----------------+------------------------------------------------------------ 615 616 ---------------------------------------------------------------------------------------------- 617 618 Chip selects: 619 620 +------+----------------+------------------------------------------------------------ 621 | # | Name | Comment 622 +------+----------------+------------------------------------------------------------ 623 | CS0 | CS0 | Boot flash 624 | CS1 | CS_FLASH | NAND flash 625 | CS2 | CS_DSP | DSP 626 | CS3 | DCS_DRAM | DRAM 627 | CS4 | CS_FLASH2 | (V2) 2nd flash 628 +------+----------------+------------------------------------------------------------ 629 630 ---------------------------------------------------------------------------------------------- 631 632 Interrupts: 633 634 +------+----------------+------------------------------------------------------------ 635 | # | Name | Comment 636 +------+----------------+------------------------------------------------------------ 637 | IRQ1 | IRQ_DSP | DSP interrupt 638 | IRQ3 | S_INTER | DUSLIC ??? 639 | IRQ4 | F_RY_BY | NAND 640 | IRQ7 | IRQ_MAX | MAX 3100 interrupt 641 +------+----------------+------------------------------------------------------------ 642 643 ---------------------------------------------------------------------------------------------- 644 645 Interrupts on PCMCIA pins: 646 647 +------+----------------+------------------------------------------------------------ 648 | # | Name | Comment 649 +------+----------------+------------------------------------------------------------ 650 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface 651 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface 652 | IP_A2| RMII1_MDINT | PHY interrupt for #1 653 | IP_A3| RMII2_MDINT | PHY interrupt for #2 654 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake 655 | IP_A6| OK_ETH | (V2) Cisco inline power OK 656 +------+----------------+------------------------------------------------------------ 657 658*************************************************************************************************/ 659 660#define CONFIG_SED156X 1 /* use SED156X */ 661#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ 662 663/* serial interfacing macros */ 664 665#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 666#define SED156X_SPI_RXD_MASK 0x00000008 667 668#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 669#define SED156X_SPI_TXD_MASK 0x00000004 670 671#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 672#define SED156X_SPI_CLK_MASK 0x00000002 673 674#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 675#define SED156X_CS_MASK 0x00000010 676 677#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) 678#define SED156X_A0_MASK 0x0020 679 680/*************************************************************************************************/ 681 682#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 683#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 684#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 685 686/*************************************************************************************************/ 687 688/* use board specific hardware */ 689#undef CONFIG_WATCHDOG /* watchdog disabled */ 690#define CONFIG_HW_WATCHDOG 691#define CONFIG_SHOW_ACTIVITY 692 693/*************************************************************************************************/ 694 695/* phone console configuration */ 696 697#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ 698 699/*************************************************************************************************/ 700 701#define CONFIG_CDP_DEVICE_ID 20 702#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ 703#define CONFIG_CDP_PORT_ID "eth%d" 704#define CONFIG_CDP_CAPABILITIES 0x00000010 705#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME 706#define CONFIG_CDP_PLATFORM "Intracom NetPhone" 707#define CONFIG_CDP_TRIGGER 0x20020001 708#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ 709#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ 710 711/*************************************************************************************************/ 712 713#define CONFIG_AUTO_COMPLETE 1 714 715/*************************************************************************************************/ 716 717#define CONFIG_CRC32_VERIFY 1 718 719/*************************************************************************************************/ 720 721#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 722 723/*************************************************************************************************/ 724#endif /* __CONFIG_H */ 725