1/* 2 * (C) Copyright 2000-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr 26 * U-Boot port on NetTA4 board 27 */ 28 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32/* 33 * High Level Configuration Options 34 * (easy to change) 35 */ 36 37#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ 38#define CONFIG_NETTA 1 /* ...on a NetTA board */ 39 40#define CONFIG_SYS_TEXT_BASE 0x40000000 41 42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 43#undef CONFIG_8xx_CONS_SMC2 44#undef CONFIG_8xx_CONS_NONE 45 46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 47 48/* #define CONFIG_XIN 10000000 */ 49#define CONFIG_XIN 50000000 50#define MPC8XX_HZ 120000000 51/* #define MPC8XX_HZ 100000000 */ 52/* #define MPC8XX_HZ 50000000 */ 53/* #define MPC8XX_HZ 80000000 */ 54 55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ 56 57#if 0 58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 59#else 60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 61#endif 62 63#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ 64 65#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 66 67#undef CONFIG_BOOTARGS 68#define CONFIG_BOOTCOMMAND \ 69 "tftpboot; " \ 70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 72 "bootm" 73 74#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 75#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 76 77#undef CONFIG_WATCHDOG /* watchdog disabled */ 78#define CONFIG_HW_WATCHDOG 79 80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 81 82/* 83 * BOOTP options 84 */ 85#define CONFIG_BOOTP_SUBNETMASK 86#define CONFIG_BOOTP_GATEWAY 87#define CONFIG_BOOTP_HOSTNAME 88#define CONFIG_BOOTP_BOOTPATH 89#define CONFIG_BOOTP_BOOTFILESIZE 90#define CONFIG_BOOTP_NISDOMAIN 91 92 93#undef CONFIG_MAC_PARTITION 94#undef CONFIG_DOS_PARTITION 95 96#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 97 98#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ 99#define FEC_ENET 1 /* eth.c needs it that way... */ 100#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */ 101#define CONFIG_MII 1 102#define CONFIG_MII_INIT 1 103#define CONFIG_RMII 1 /* use RMII interface */ 104 105#if defined(CONFIG_NETTA_ISDN) 106#define CONFIG_ETHER_ON_FEC1 1 107#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ 108#define CONFIG_FEC1_PHY_NORXERR 1 109#undef CONFIG_ETHER_ON_FEC2 110#else 111#define CONFIG_ETHER_ON_FEC1 1 112#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ 113#define CONFIG_FEC1_PHY_NORXERR 1 114#define CONFIG_ETHER_ON_FEC2 1 115#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ 116#define CONFIG_FEC2_PHY_NORXERR 1 117#endif 118 119#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ 120 121/* POST support */ 122#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 123 CONFIG_SYS_POST_CODEC | \ 124 CONFIG_SYS_POST_DSP ) 125 126 127/* 128 * Command line configuration. 129 */ 130#include <config_cmd_default.h> 131 132#define CONFIG_CMD_CDP 133#define CONFIG_CMD_DHCP 134#define CONFIG_CMD_DIAG 135#define CONFIG_CMD_FAT 136#define CONFIG_CMD_IDE 137#define CONFIG_CMD_JFFS2 138#define CONFIG_CMD_MII 139#define CONFIG_CMD_NFS 140#define CONFIG_CMD_PCMCIA 141#define CONFIG_CMD_PING 142 143 144#define CONFIG_BOARD_EARLY_INIT_F 1 145#define CONFIG_MISC_INIT_R 146 147/* 148 * Miscellaneous configurable options 149 */ 150#define CONFIG_SYS_LONGHELP /* undef to save memory */ 151#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 152 153#define CONFIG_SYS_HUSH_PARSER 1 154#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 155 156#if defined(CONFIG_CMD_KGDB) 157#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 158#else 159#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 160#endif 161#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 162#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 163#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 164 165#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ 166#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ 167 168#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 169 170#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 171 172#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 173 174/* 175 * Low Level Configuration Settings 176 * (address mappings, register initial values, etc.) 177 * You should know what you are doing if you make changes here. 178 */ 179/*----------------------------------------------------------------------- 180 * Internal Memory Mapped Register 181 */ 182#define CONFIG_SYS_IMMR 0xFF000000 183 184/*----------------------------------------------------------------------- 185 * Definitions for initial stack pointer and data area (in DPRAM) 186 */ 187#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 188#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ 189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192/*----------------------------------------------------------------------- 193 * Start addresses for the final memory configuration 194 * (Set up by the startup code) 195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 196 */ 197#define CONFIG_SYS_SDRAM_BASE 0x00000000 198#define CONFIG_SYS_FLASH_BASE 0x40000000 199#if defined(DEBUG) 200#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 201#else 202#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 203#endif 204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 205#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 206 207/* 208 * For booting Linux, the board info and command line data 209 * have to be in the first 8 MB of memory, since this is 210 * the maximum mapped by the Linux kernel during initialization. 211 */ 212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 213 214/*----------------------------------------------------------------------- 215 * FLASH organization 216 */ 217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 218#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 219 220#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 221#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 222 223#define CONFIG_ENV_IS_IN_FLASH 1 224#define CONFIG_ENV_SECT_SIZE 0x10000 225 226#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) 227#define CONFIG_ENV_SIZE 0x4000 228 229#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) 230#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 231 232/*----------------------------------------------------------------------- 233 * Cache Configuration 234 */ 235#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 236#if defined(CONFIG_CMD_KGDB) 237#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 238#endif 239 240/*----------------------------------------------------------------------- 241 * SYPCR - System Protection Control 11-9 242 * SYPCR can only be written once after reset! 243 *----------------------------------------------------------------------- 244 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 245 */ 246#if defined(CONFIG_WATCHDOG) 247#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 248 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 249#else 250#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 251#endif 252 253/*----------------------------------------------------------------------- 254 * SIUMCR - SIU Module Configuration 11-6 255 *----------------------------------------------------------------------- 256 * PCMCIA config., multi-function pin tri-state 257 */ 258#ifndef CONFIG_CAN_DRIVER 259#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 260#else /* we must activate GPL5 in the SIUMCR for CAN */ 261#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 262#endif /* CONFIG_CAN_DRIVER */ 263 264/*----------------------------------------------------------------------- 265 * TBSCR - Time Base Status and Control 11-26 266 *----------------------------------------------------------------------- 267 * Clear Reference Interrupt Status, Timebase freezing enabled 268 */ 269#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 270 271/*----------------------------------------------------------------------- 272 * RTCSC - Real-Time Clock Status and Control Register 11-27 273 *----------------------------------------------------------------------- 274 */ 275#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 276 277/*----------------------------------------------------------------------- 278 * PISCR - Periodic Interrupt Status and Control 11-31 279 *----------------------------------------------------------------------- 280 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 281 */ 282#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 283 284/*----------------------------------------------------------------------- 285 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 286 *----------------------------------------------------------------------- 287 * Reset PLL lock status sticky bit, timer expired status bit and timer 288 * interrupt status bit 289 * 290 */ 291 292#if CONFIG_XIN == 10000000 293 294#if MPC8XX_HZ == 120000000 295#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 296 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 297 PLPRCR_TEXPS) 298#elif MPC8XX_HZ == 100000000 299#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 300 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 301 PLPRCR_TEXPS) 302#elif MPC8XX_HZ == 50000000 303#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 304 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 305 PLPRCR_TEXPS) 306#elif MPC8XX_HZ == 25000000 307#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 308 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ 309 PLPRCR_TEXPS) 310#elif MPC8XX_HZ == 40000000 311#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 312 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 313 PLPRCR_TEXPS) 314#elif MPC8XX_HZ == 75000000 315#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 316 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ 317 PLPRCR_TEXPS) 318#else 319#error unsupported CPU freq for XIN = 10MHz 320#endif 321 322#elif CONFIG_XIN == 50000000 323 324#if MPC8XX_HZ == 120000000 325#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 326 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 327 PLPRCR_TEXPS) 328#elif MPC8XX_HZ == 100000000 329#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 330 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 331 PLPRCR_TEXPS) 332#elif MPC8XX_HZ == 80000000 333#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 334 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ 335 PLPRCR_TEXPS) 336#elif MPC8XX_HZ == 50000000 337#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ 338 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ 339 PLPRCR_TEXPS) 340#else 341#error unsupported CPU freq for XIN = 50MHz 342#endif 343 344#else 345 346#error unsupported XIN freq 347#endif 348 349 350/* 351 *----------------------------------------------------------------------- 352 * SCCR - System Clock and reset Control Register 15-27 353 *----------------------------------------------------------------------- 354 * Set clock output, timebase and RTC source and divider, 355 * power management and some other internal clocks 356 * 357 * Note: When TBS == 0 the timebase is independent of current cpu clock. 358 */ 359 360#define SCCR_MASK SCCR_EBDF11 361#if MPC8XX_HZ > 66666666 362#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 363 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 364 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 365 SCCR_DFALCD00 | SCCR_EBDF01) 366#else 367#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ 368 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 369 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 370 SCCR_DFALCD00) 371#endif 372 373/*----------------------------------------------------------------------- 374 * 375 *----------------------------------------------------------------------- 376 * 377 */ 378/*#define CONFIG_SYS_DER 0x2002000F*/ 379#define CONFIG_SYS_DER 0 380 381/* 382 * Init Memory Controller: 383 * 384 * BR0/1 and OR0/1 (FLASH) 385 */ 386 387#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 388 389/* used to re-map FLASH both when starting from SRAM or FLASH: 390 * restrict access enough to keep SRAM working (if any) 391 * but not too much to meddle with FLASH accesses 392 */ 393#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 394#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 395 396/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 397#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) 398 399#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 400#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 401#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 402 403/* 404 * BR3 and OR3 (SDRAM) 405 * 406 */ 407#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ 408#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ 409 410/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 411#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) 412 413#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) 414#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) 415 416/* 417 * Memory Periodic Timer Prescaler 418 */ 419 420/* 421 * Memory Periodic Timer Prescaler 422 * 423 * The Divider for PTA (refresh timer) configuration is based on an 424 * example SDRAM configuration (64 MBit, one bank). The adjustment to 425 * the number of chip selects (NCS) and the actually needed refresh 426 * rate is done by setting MPTPR. 427 * 428 * PTA is calculated from 429 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 430 * 431 * gclk CPU clock (not bus clock!) 432 * Trefresh Refresh cycle * 4 (four word bursts used) 433 * 434 * 4096 Rows from SDRAM example configuration 435 * 1000 factor s -> ms 436 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 437 * 4 Number of refresh cycles per period 438 * 64 Refresh cycle in ms per number of rows 439 * -------------------------------------------- 440 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 441 * 442 * 50 MHz => 50.000.000 / Divider = 98 443 * 66 Mhz => 66.000.000 / Divider = 129 444 * 80 Mhz => 80.000.000 / Divider = 156 445 */ 446 447#if MPC8XX_HZ == 120000000 448#define CONFIG_SYS_MAMR_PTA 234 449#elif MPC8XX_HZ == 100000000 450#define CONFIG_SYS_MAMR_PTA 195 451#elif MPC8XX_HZ == 80000000 452#define CONFIG_SYS_MAMR_PTA 156 453#elif MPC8XX_HZ == 50000000 454#define CONFIG_SYS_MAMR_PTA 98 455#else 456#error Unknown frequency 457#endif 458 459 460/* 461 * For 16 MBit, refresh rates could be 31.3 us 462 * (= 64 ms / 2K = 125 / quad bursts). 463 * For a simpler initialization, 15.6 us is used instead. 464 * 465 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 466 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 467 */ 468#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 469#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 470 471/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 472#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 473#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 474 475/* 476 * MAMR settings for SDRAM 477 */ 478 479/* 8 column SDRAM */ 480#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 481 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 482 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 483 484/* 9 column SDRAM */ 485#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 486 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 487 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 488 489#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ 490 491/*********************************************************************************************************** 492 493 Pin definitions: 494 495 +------+----------------+--------+------------------------------------------------------------ 496 | # | Name | Type | Comment 497 +------+----------------+--------+------------------------------------------------------------ 498 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK 499 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) 500 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA 501 | PA7 | DCL1_3V | Periph | IDL1 PCM clock 502 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx 503 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx 504 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA 505 | PA12 | P_SHDN | Output | TPS2211A PCMCIA 506 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power 507 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) 508 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA 509 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA 510 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board 511 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) 512 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. 513 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC 514 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC 515 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) 516 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom 517 | PB21 | LEDIO | Output | Led mode indication for PHY 518 | PB22 | UART_CTS | Input | UART CTS 519 | PB23 | UART_RTS | Output | UART RTS 520 | PB24 | UART_RX | Periph | UART Data Rx 521 | PB25 | UART_TX | Periph | UART Data Tx 522 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) 523 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) 524 | PB28 | SPI_RXD_3V | Input | SPI Data Rx 525 | PB29 | SPI_TXD | Output | SPI Data Tx 526 | PB30 | SPI_CLK | Output | SPI Clock 527 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 528 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) 529 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) 530 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) 531 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) 532 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) 533 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) 534 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) 535 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) 536 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) 537 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) 538 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) 539 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. 540 | PD3 | F_ALE | Output | NAND 541 | PD4 | F_CLE | Output | NAND 542 | PD5 | F_CE | Output | NAND 543 | PD6 | DSP_INT | Output | DSP debug interrupt 544 | PD7 | DSP_RESET | Output | DSP reset 545 | PD8 | RMII_MDC | Periph | MII mgt clock 546 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 547 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 548 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 549 | PD12 | FSC2 | Periph | IDL2 frame sync 550 | PD13 | DGRANT2 | Input | D channel grant from S #2 551 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 552 | PD15 | TP700 | Output | Testpoint for software debugging 553 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data 554 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data 555 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for 556 | | DCL2 | Periph | NetRoute: PCM clock #2 557 | PE17 | TP703 | Output | Testpoint for software debugging 558 | PE18 | DGRANT1 | Input | D channel grant from S #1 559 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable 560 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 561 | PE20 | FSC1 | Periph | IDL1 frame sync 562 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data 563 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data 564 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC 565 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) 566 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) 567 | PE26 | RMII2-RXDV | Periph | FEC2 valid 568 | PE27 | DREQ2 | Output | D channel request for S #2. 569 | PE28 | FPGA_DONE | Input | FPGA done signal 570 | PE29 | FPGA_INIT | Output | FPGA init signal 571 | PE30 | UDOUT2_3V | Input | IDL2 PCM input 572 | PE31 | | | Free 573 +------+----------------+--------+--------------------------------------------------- 574 575 Chip selects: 576 577 +------+----------------+------------------------------------------------------------ 578 | # | Name | Comment 579 +------+----------------+------------------------------------------------------------ 580 | CS0 | CS0 | Boot flash 581 | CS1 | CS_FLASH | NAND flash 582 | CS2 | CS_DSP | DSP 583 | CS3 | DCS_DRAM | DRAM 584 | CS4 | CS_ER1 | External output register 585 +------+----------------+------------------------------------------------------------ 586 587 Interrupts: 588 589 +------+----------------+------------------------------------------------------------ 590 | # | Name | Comment 591 +------+----------------+------------------------------------------------------------ 592 | IRQ1 | UINTER_3V | S interupt chips interrupt (common) 593 | IRQ3 | IRQ_DSP | DSP interrupt 594 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt 595 +------+----------------+------------------------------------------------------------ 596 597*************************************************************************************************/ 598 599#define DSP_SIZE 0x00010000 /* 64K */ 600#define NAND_SIZE 0x00010000 /* 64K */ 601#define ER_SIZE 0x00010000 /* 64K */ 602#define DUMMY_SIZE 0x00010000 /* 64K */ 603 604#define DSP_BASE 0xF1000000 605#define NAND_BASE 0xF1010000 606#define ER_BASE 0xF1020000 607#define DUMMY_BASE 0xF1FF0000 608 609/*****************************************************************************/ 610 611#define CONFIG_SYS_DIRECT_FLASH_TFTP 612#define CONFIG_SYS_DIRECT_NAND_TFTP 613 614/*****************************************************************************/ 615 616#if 1 617/*----------------------------------------------------------------------- 618 * PCMCIA stuff 619 *----------------------------------------------------------------------- 620 */ 621 622#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 623#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 624#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 625#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 626#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 627#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 628#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 629#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 630 631/*----------------------------------------------------------------------- 632 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 633 *----------------------------------------------------------------------- 634 */ 635 636#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 637 638#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 639#undef CONFIG_IDE_LED /* LED for ide not supported */ 640#undef CONFIG_IDE_RESET /* reset for ide not supported */ 641 642#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 643#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 644 645#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 646 647#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 648 649/* Offset for data I/O */ 650#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 651 652/* Offset for normal register accesses */ 653#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 654 655/* Offset for alternate registers */ 656#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 657 658#define CONFIG_MAC_PARTITION 659#define CONFIG_DOS_PARTITION 660#endif 661 662/*************************************************************************************************/ 663 664#define CONFIG_CDP_DEVICE_ID 20 665#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ 666#define CONFIG_CDP_PORT_ID "eth%d" 667#define CONFIG_CDP_CAPABILITIES 0x00000010 668#define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME 669#define CONFIG_CDP_PLATFORM "Intracom NetTA" 670#define CONFIG_CDP_TRIGGER 0x20020001 671#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ 672#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ 673 674/*************************************************************************************************/ 675 676#define CONFIG_AUTO_COMPLETE 1 677 678/*************************************************************************************************/ 679 680#define CONFIG_CRC32_VERIFY 1 681 682/*************************************************************************************************/ 683 684#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 685 686/*************************************************************************************************/ 687 688#endif /* __CONFIG_H */ 689