LXR uboot/include/configs/PMC405DE.h

   1/*
   2 * (C) Copyright 2009
   3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  28#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  29#define CONFIG_PMC405DE         1       /* ...on a PMC405DE board       */
  30
  31#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  32
  33#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  34#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  35#define CONFIG_BOARD_TYPES      1       /* support board types          */
  36
  37#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  38
  39#define CONFIG_BAUDRATE         115200
  40#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  41
  42#undef  CONFIG_BOOTARGS
  43#undef  CONFIG_BOOTCOMMAND
  44
  45#define CONFIG_PREBOOT                  /* enable preboot variable      */
  46
  47#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change*/
  48
  49#define CONFIG_NET_MULTI        1
  50#define CONFIG_HAS_ETH1
  51
  52#define CONFIG_PPC4xx_EMAC
  53#define CONFIG_MII              1       /* MII PHY management           */
  54#define CONFIG_PHY_ADDR         1       /* PHY address                  */
  55#define CONFIG_PHY1_ADDR        2       /* 2nd PHY address              */
  56
  57#define CONFIG_SYS_RX_ETH_BUFFER        16 /* use 16 rx buffer on 405 emac */
  58
  59/*
  60 * BOOTP options
  61 */
  62#define CONFIG_BOOTP_SUBNETMASK
  63#define CONFIG_BOOTP_GATEWAY
  64#define CONFIG_BOOTP_HOSTNAME
  65#define CONFIG_BOOTP_BOOTPATH
  66#define CONFIG_BOOTP_DNS
  67#define CONFIG_BOOTP_DNS2
  68#define CONFIG_BOOTP_SEND_HOSTNAME
  69
  70/*
  71 * Command line configuration.
  72 */
  73#include <config_cmd_default.h>
  74
  75#define CONFIG_CMD_BSP
  76#define CONFIG_CMD_CHIP_CONFIG
  77#define CONFIG_CMD_DATE
  78#define CONFIG_CMD_DHCP
  79#define CONFIG_CMD_EEPROM
  80#define CONFIG_CMD_ELF
  81#define CONFIG_CMD_I2C
  82#define CONFIG_CMD_IRQ
  83#define CONFIG_CMD_MII
  84#define CONFIG_CMD_NFS
  85#define CONFIG_CMD_PCI
  86#define CONFIG_CMD_PING
  87
  88#define CONFIG_OF_LIBFDT
  89#define CONFIG_OF_BOARD_SETUP
  90
  91#undef  CONFIG_WATCHDOG                 /* watchdog disabled */
  92#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  93#define CONFIG_PRAM             0
  94
  95/*
  96 * Miscellaneous configurable options
  97 */
  98#define CONFIG_SYS_LONGHELP
  99#define CONFIG_SYS_PROMPT       "=> "   /* Monitor Command Prompt */
 100
 101#define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 103#define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 104#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 105
 106#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
 107#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console info */
 108
 109#define CONFIG_SYS_MEMTEST_START        0x0100000 /* memtest works on */
 110#define CONFIG_SYS_MEMTEST_END          0x3000000 /* 1 ... 48 MB in DRAM */
 111
 112#define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 113#define CONFIG_SYS_NS16550
 114#define CONFIG_SYS_NS16550_SERIAL
 115#define CONFIG_SYS_NS16550_REG_SIZE     1
 116#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 117
 118#undef  CONFIG_SYS_EXT_SERIAL_CLOCK
 119#define CONFIG_SYS_BASE_BAUD            691200
 120
 121/* The following table includes the supported baudrates */
 122#define CONFIG_SYS_BAUDRATE_TABLE       \
 123        { 9600, 19200, 38400, 57600, 115200 }
 124
 125#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 126#define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
 127
 128#define CONFIG_SYS_HZ           1000    /* decrementer freq: 1 ms ticks */
 129
 130#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 131#define CONFIG_LOOPW            1       /* enable loopw command         */
 132#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 133#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 134#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 135
 136#define CONFIG_AUTOBOOT_KEYED   1
 137#define CONFIG_AUTOBOOT_PROMPT  \
 138        "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 139#undef CONFIG_AUTOBOOT_DELAY_STR
 140#define CONFIG_AUTOBOOT_STOP_STR " "
 141
 142/*
 143 * PCI stuff
 144 */
 145#define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 146#define PCI_HOST_FORCE          1       /* configure as pci host        */
 147#define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 148
 149#define CONFIG_PCI              /* include pci support                  */
 150#define CONFIG_PCI_HOST PCI_HOST_AUTO  /* select pci host function      */
 151#define CONFIG_PCI_PNP          /* do (not) pci plug-and-play           */
 152
 153#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup          */
 154
 155/*
 156 * PCI identification
 157 */
 158#define CONFIG_SYS_PCI_SUBSYS_VENDORID          PCI_VENDOR_ID_ESDGMBH
 159#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
 160#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
 161#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 162#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 163
 164#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
 165#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 166
 167#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
 168#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
 169#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
 170#define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
 171#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
 172#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
 173
 174#define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 175
 176/*
 177 * For booting Linux, the board info and command line data
 178 * have to be in the first 8 MB of memory, since this is
 179 * the maximum mapped by the Linux kernel during initialization.
 180 */
 181#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 182/*
 183 * FLASH organization
 184 */
 185#define CONFIG_SYS_FLASH_CFI            1       /* CFI compatible */
 186#define CONFIG_FLASH_CFI_DRIVER         1       /* Use common CFI driver */
 187
 188#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 189
 190#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max. no. memory banks */
 191#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per chip */
 192
 193#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* erase timeout (in ms) */
 194#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* write timeout (in ms) */
 195
 196#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buffered writes (faster) */
 197#define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection */
 198
 199#define CONFIG_SYS_FLASH_EMPTY_INFO     1 /* 'E' for empty sector (flinfo) */
 200#define CONFIG_SYS_FLASH_QUIET_TEST     1 /* don't warn upon unknown flash */
 201
 202
 203/*
 204 * Start addresses for the final memory configuration
 205 * (Set up by the startup code)
 206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 207 */
 208#define CONFIG_SYS_SDRAM_BASE           0x00000000
 209#define CONFIG_SYS_FLASH_BASE           0xfe000000
 210#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 211#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 212#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 213
 214/*
 215 * Environment in EEPROM setup
 216 */
 217#define CONFIG_ENV_IS_IN_EEPROM         1
 218#define CONFIG_ENV_OFFSET               0x100
 219#define CONFIG_ENV_SIZE                 0x700
 220
 221/*
 222 * I2C EEPROM (24W16) for environment
 223 */
 224#define CONFIG_HARD_I2C                 /* I2c with hardware support */
 225#define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 226#define CONFIG_SYS_I2C_SPEED            400000 /* I2C speed and slave address */
 227#define CONFIG_SYS_I2C_SLAVE            0x7F
 228
 229#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM 24W16 */
 230#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 231/* mask of address bits that overflow into the "EEPROM chip address" */
 232#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 233#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has */
 234                                        /* 16 byte page write mode using*/
 235                                        /* last 4 bits of the address */
 236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 237#define CONFIG_SYS_EEPROM_WREN          1
 238
 239#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 240#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0x40
 241#define CONFIG_4xx_CONFIG_BLOCKSIZE             0x20
 242
 243/*
 244 * RTC
 245 */
 246#define CONFIG_RTC_RX8025
 247
 248/*
 249 * External Bus Controller (EBC) Setup
 250 * (max. 55MHZ EBC clock)
 251 */
 252/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
 253#define CONFIG_SYS_EBC_PB0AP            0x03017200
 254#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xba000)
 255
 256/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
 257#define CONFIG_SYS_CPLD_BASE            0xef000000
 258#define CONFIG_SYS_EBC_PB1AP            0x00800000
 259#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 260
 261/*
 262 * Definitions for initial stack pointer and data area (in data cache)
 263 */
 264/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 265#define CONFIG_SYS_TEMP_STACK_OCM         1
 266
 267/* On Chip Memory location */
 268#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 269#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 270/* inside SDRAM */
 271#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 272/* End of used area in RAM */
 273#define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 274
 275#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 276                                         GENERATED_GBL_DATA_SIZE)
 277#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 278
 279/*
 280 * GPIO Configuration
 281 */
 282#define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
 283{                                                                             \
 284/* GPIO Core 0 */                                                             \
 285{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 286{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 287{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 288{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 289{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 290{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
 291{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
 292{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
 293{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 294{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
 295{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 296{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 297{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 298{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 299{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 300{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 301{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 302{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 303{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 304{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 305{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 306{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 307{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 308{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 309{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 310{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 311{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 312{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 313{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 314{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 315{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 316{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 317}                                                                             \
 318}
 319
 320#define CONFIG_SYS_GPIO_HWREV_MASK      (0xf0000000 >> 1)       /* GPIO1..4 */
 321#define CONFIG_SYS_GPIO_HWREV_SHIFT     27
 322#define CONFIG_SYS_GPIO_LEDRUN_N        (0x80000000 >> 5)       /* GPIO5 */
 323#define CONFIG_SYS_GPIO_LEDA_N          (0x80000000 >> 6)       /* GPIO6 */
 324#define CONFIG_SYS_GPIO_LEDB_N          (0x80000000 >> 7)       /* GPIO7 */
 325#define CONFIG_SYS_GPIO_SELFRST_N       (0x80000000 >> 8)       /* GPIO8 */
 326#define CONFIG_SYS_GPIO_EEPROM_WP       (0x80000000 >> 9)       /* GPIO9 */
 327#define CONFIG_SYS_GPIO_MONARCH_N       (0x80000000 >> 11)      /* GPIO11 */
 328#define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 12)      /* GPIO12 */
 329#define CONFIG_SYS_GPIO_M66EN           (0x80000000 >> 13)      /* GPIO13 */
 330
 331/*
 332 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 333 * This value will be set if iic boot eprom is disabled.
 334 */
 335#undef CONFIG_SYS_FCPU333MHZ
 336#define CONFIG_SYS_FCPU266MHZ
 337#undef CONFIG_SYS_FCPU133MHZ
 338
 339#if defined(CONFIG_SYS_FCPU333MHZ)
 340/*
 341 * CPU: 333MHz
 342 * PLB/SDRAM/MAL: 111MHz
 343 * OPB: 55MHz
 344 * EBC: 55MHz
 345 * PCI: 55MHz (111MHz on M66EN=1)
 346 */
 347#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |           \
 348                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |        \
 349                        PLL_MALDIV_1 | PLL_PCIDIV_2)
 350#define PLLMR1_DEFAULT (PLL_FBKDIV_10  |                        \
 351                        PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 352                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 353#endif
 354
 355#if defined(CONFIG_SYS_FCPU266MHZ)
 356/*
 357 * CPU: 266MHz
 358 * PLB/SDRAM/MAL: 133MHz
 359 * OPB: 66MHz
 360 * EBC: 44MHz
 361 * PCI: 44MHz (66MHz on M66EN=1)
 362 */
 363#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |           \
 364                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 365                        PLL_MALDIV_1 | PLL_PCIDIV_3)
 366#define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
 367                        PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |         \
 368                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 369#endif
 370
 371#if defined(CONFIG_SYS_FCPU133MHZ)
 372/*
 373 * CPU: 133MHz
 374 * PLB/SDRAM/MAL: 133MHz
 375 * OPB: 66MHz
 376 * EBC: 44MHz
 377 * PCI: 44MHz (66MHz on M66EN=1)
 378 */
 379#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |           \
 380                        PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |        \
 381                        PLL_MALDIV_1 | PLL_PCIDIV_3)
 382#define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
 383                        PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |         \
 384                        PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 385#endif
 386
 387#endif /* __CONFIG_H */
 388