1#ifndef __CONFIG_H 2#define __CONFIG_H 3 4#define CONFIG_SYS_TEXT_BASE 0x80F00000 5 6/***************************************************************************** 7 * 8 * These settings must match the way _your_ board is set up 9 * 10 *****************************************************************************/ 11/* for the AY-Revision which does not use the HRCW */ 12#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 13 14/* What is the oscillator's (UX2) frequency in Hz? */ 15#define CONFIG_8260_CLKIN (66 * 1000 * 1000) 16 17/* How is switch S2 set? We really only want the MODCK[1-3] bits, so 18 * only the 3 least significant bits are important. 19*/ 20#define CONFIG_SYS_SBC_S2 0x04 21 22/* What should MODCK_H be? It is dependent on the oscillator 23 * frequency, MODCK[1-3], and desired CPM and core frequencies. 24 * Some example values (all frequencies are in MHz): 25 * 26 * MODCK_H MODCK[1-3] Osc CPM Core 27 * 0x2 0x2 33 133 133 28 * 0x2 0x4 33 133 200 29 * 0x5 0x5 66 133 133 30 * 0x5 0x7 66 133 200 31 */ 32#define CONFIG_SYS_SBC_MODCK_H 0x06 33 34#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */ 35#undef CONFIG_SYS_SBC_BOOT_LOW 36 37/* What should the base address of the main FLASH be and how big is 38 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk 39 * The main FLASH is whichever is connected to *CS0. U-Boot expects 40 * this to be the SIMM. 41 */ 42#define CONFIG_SYS_FLASH0_BASE 0x80000000 43#define CONFIG_SYS_FLASH0_SIZE 16 44 45/* What should the base address of the secondary FLASH be and how big 46 * is it (in Mbytes)? The secondary FLASH is whichever is connected 47 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't 48 * want it enabled, don't define these constants. 49 */ 50#define CONFIG_SYS_FLASH1_BASE 0 51#define CONFIG_SYS_FLASH1_SIZE 0 52#undef CONFIG_SYS_FLASH1_BASE 53#undef CONFIG_SYS_FLASH1_SIZE 54 55/* What should be the base address of SDRAM DIMM and how big is 56 * it (in Mbytes)? 57*/ 58#define CONFIG_SYS_SDRAM0_BASE 0x00000000 59#define CONFIG_SYS_SDRAM0_SIZE 64 60 61/* What should be the base address of SDRAM DIMM and how big is 62 * it (in Mbytes)? 63*/ 64#define CONFIG_SYS_SDRAM1_BASE 0x04000000 65#define CONFIG_SYS_SDRAM1_SIZE 32 66 67/* What should be the base address of the LEDs and switch S0? 68 * If you don't want them enabled, don't define this. 69 */ 70#define CONFIG_SYS_LED_BASE 0x00000000 71 72/* 73 * select serial console configuration 74 * 75 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 76 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 77 * for SCC). 78 * 79 * if CONFIG_CONS_NONE is defined, then the serial console routines must 80 * defined elsewhere. 81 */ 82#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 83#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 84#undef CONFIG_CONS_NONE /* define if console on neither */ 85#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ 86 87/* 88 * select ethernet configuration 89 * 90 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 91 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 92 * for FCC) 93 * 94 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 95 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 96 */ 97#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ 98#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ 99#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ 100#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ 101 102#if ( CONFIG_ETHER_INDEX == 3 ) 103 104/* 105 * - Rx-CLK is CLK15 106 * - Tx-CLK is CLK16 107 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 108 * - Enable Half Duplex in FSMR 109 */ 110# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) 111# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) 112# define CONFIG_SYS_CPMFCR_RAMTYPE 0 113/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ 114# define CONFIG_SYS_FCC_PSMR 0 115 116#else /* CONFIG_ETHER_INDEX */ 117# error "on RPX Super ethernet must be FCC3" 118#endif /* CONFIG_ETHER_INDEX */ 119 120#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 121#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 122#define CONFIG_SYS_I2C_SLAVE 0x7F 123 124 125/* Define this to reserve an entire FLASH sector (256 KB) for 126 * environment variables. Otherwise, the environment will be 127 * put in the same sector as U-Boot, and changing variables 128 * will erase U-Boot temporarily 129 */ 130#define CONFIG_ENV_IN_OWN_SECT 131 132/* Define to allow the user to overwrite serial and ethaddr */ 133#define CONFIG_ENV_OVERWRITE 134 135/* What should the console's baud rate be? */ 136#define CONFIG_BAUDRATE 115200 137 138/* Ethernet MAC address */ 139#define CONFIG_ETHADDR 08:00:22:50:70:63 140 141#define CONFIG_IPADDR 192.168.1.99 142#define CONFIG_SERVERIP 192.168.1.3 143 144/* Set to a positive value to delay for running BOOTCOMMAND */ 145#define CONFIG_BOOTDELAY -1 146 147/* undef this to save memory */ 148#define CONFIG_SYS_LONGHELP 149 150/* Monitor Command Prompt */ 151#define CONFIG_SYS_PROMPT "=> " 152 153 154/* 155 * BOOTP options 156 */ 157#define CONFIG_BOOTP_BOOTFILESIZE 158#define CONFIG_BOOTP_BOOTPATH 159#define CONFIG_BOOTP_GATEWAY 160#define CONFIG_BOOTP_HOSTNAME 161 162 163/* 164 * Command line configuration. 165 */ 166#include <config_cmd_default.h> 167 168#define CONFIG_CMD_IMMAP 169#define CONFIG_CMD_ASKENV 170#define CONFIG_CMD_I2C 171#define CONFIG_CMD_REGINFO 172 173#undef CONFIG_CMD_KGDB 174 175 176/* Where do the internal registers live? */ 177#define CONFIG_SYS_IMMR 0xF0000000 178 179/* Where do the on board registers (CS4) live? */ 180#define CONFIG_SYS_REGS_BASE 0xFA000000 181 182/***************************************************************************** 183 * 184 * You should not have to modify any of the following settings 185 * 186 *****************************************************************************/ 187 188#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 189#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ 190#define CONFIG_CPM2 1 /* Has a CPM2 */ 191 192#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 193#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 194 195/* 196 * Miscellaneous configurable options 197 */ 198#if defined(CONFIG_CMD_KGDB) 199# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 200#else 201# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 202#endif 203 204/* Print Buffer Size */ 205#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 206 207#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ 208 209#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 210 211#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ 212#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ 213 214#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 215 216#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 217#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 218 219/* valid baudrates */ 220#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 221 222/* 223 * Low Level Configuration Settings 224 * (address mappings, register initial values, etc.) 225 * You should know what you are doing if you make changes here. 226 */ 227 228#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 229#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE 230 231/*----------------------------------------------------------------------- 232 * Hard Reset Configuration Words 233 */ 234#if defined(CONFIG_SYS_SBC_BOOT_LOW) 235# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) 236#else 237# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) 238#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ 239 240/* get the HRCW ISB field from CONFIG_SYS_IMMR */ 241#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ 242 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ 243 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) 244 245#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\ 246 HRCW_DPPC11 |\ 247 CONFIG_SYS_SBC_HRCW_IMMR |\ 248 HRCW_MMR00 |\ 249 HRCW_LBPC11 |\ 250 HRCW_APPC10 |\ 251 HRCW_CS10PC00 |\ 252 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\ 253 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) 254 255/* no slaves */ 256#define CONFIG_SYS_HRCW_SLAVE1 0 257#define CONFIG_SYS_HRCW_SLAVE2 0 258#define CONFIG_SYS_HRCW_SLAVE3 0 259#define CONFIG_SYS_HRCW_SLAVE4 0 260#define CONFIG_SYS_HRCW_SLAVE5 0 261#define CONFIG_SYS_HRCW_SLAVE6 0 262#define CONFIG_SYS_HRCW_SLAVE7 0 263 264/*----------------------------------------------------------------------- 265 * Definitions for initial stack pointer and data area (in DPRAM) 266 */ 267#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 268#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 270#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 271 272/*----------------------------------------------------------------------- 273 * Start addresses for the final memory configuration 274 * (Set up by the startup code) 275 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 276 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. 277 */ 278#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000) 279 280#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 281# define CONFIG_SYS_RAMBOOT 282#endif 283 284#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 285#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 286 287/* 288 * For booting Linux, the board info and command line data 289 * have to be in the first 8 MB of memory, since this is 290 * the maximum mapped by the Linux kernel during initialization. 291 */ 292#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 293 294/*----------------------------------------------------------------------- 295 * FLASH and environment organization 296 */ 297#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 298#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 299 300#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ 301#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ 302 303#ifndef CONFIG_SYS_RAMBOOT 304# define CONFIG_ENV_IS_IN_FLASH 1 305 306# ifdef CONFIG_ENV_IN_OWN_SECT 307# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 308# define CONFIG_ENV_SECT_SIZE 0x40000 309# else 310# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) 311# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 312# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ 313# endif /* CONFIG_ENV_IN_OWN_SECT */ 314#else 315# define CONFIG_ENV_IS_IN_NVRAM 1 316# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 317# define CONFIG_ENV_SIZE 0x200 318#endif /* CONFIG_SYS_RAMBOOT */ 319 320/*----------------------------------------------------------------------- 321 * Cache Configuration 322 */ 323#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 324 325#if defined(CONFIG_CMD_KGDB) 326# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 327#endif 328 329/*----------------------------------------------------------------------- 330 * HIDx - Hardware Implementation-dependent Registers 2-11 331 *----------------------------------------------------------------------- 332 * HID0 also contains cache control - initially enable both caches and 333 * invalidate contents, then the final state leaves only the instruction 334 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 335 * but Soft reset does not. 336 * 337 * HID1 has only read-only information - nothing to set. 338 */ 339#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\ 340 /*HID0_DCE |*/\ 341 HID0_ICFI |\ 342 HID0_DCI |\ 343 HID0_IFEM |\ 344 HID0_ABE) 345 346#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ 347 HID0_IFEM |\ 348 HID0_ABE |\ 349 HID0_EMCP) 350#define CONFIG_SYS_HID2 0 351 352/*----------------------------------------------------------------------- 353 * RMR - Reset Mode Register 354 *----------------------------------------------------------------------- 355 */ 356#define CONFIG_SYS_RMR 0 357 358/*----------------------------------------------------------------------- 359 * BCR - Bus Configuration 4-25 360 *----------------------------------------------------------------------- 361 */ 362#define CONFIG_SYS_BCR (BCR_EBM |\ 363 BCR_PLDP |\ 364 BCR_EAV |\ 365 BCR_NPQM0) 366 367/*----------------------------------------------------------------------- 368 * SIUMCR - SIU Module Configuration 4-31 369 *----------------------------------------------------------------------- 370 */ 371 372#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ 373 SIUMCR_APPC10 |\ 374 SIUMCR_CS10PC01) 375 376 377/*----------------------------------------------------------------------- 378 * SYPCR - System Protection Control 11-9 379 * SYPCR can only be written once after reset! 380 *----------------------------------------------------------------------- 381 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 382 */ 383#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ 384 SYPCR_BMT |\ 385 SYPCR_PBME |\ 386 SYPCR_LBME |\ 387 SYPCR_SWRI |\ 388 SYPCR_SWP) 389 390/*----------------------------------------------------------------------- 391 * TMCNTSC - Time Counter Status and Control 4-40 392 *----------------------------------------------------------------------- 393 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 394 * and enable Time Counter 395 */ 396#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ 397 TMCNTSC_ALR |\ 398 TMCNTSC_TCF |\ 399 TMCNTSC_TCE) 400 401/*----------------------------------------------------------------------- 402 * PISCR - Periodic Interrupt Status and Control 4-42 403 *----------------------------------------------------------------------- 404 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 405 * Periodic timer 406 */ 407#define CONFIG_SYS_PISCR (PISCR_PS |\ 408 PISCR_PTF |\ 409 PISCR_PTE) 410 411/*----------------------------------------------------------------------- 412 * SCCR - System Clock Control 9-8 413 *----------------------------------------------------------------------- 414 */ 415#define CONFIG_SYS_SCCR (SCCR_DFBRG01) 416 417/*----------------------------------------------------------------------- 418 * RCCR - RISC Controller Configuration 13-7 419 *----------------------------------------------------------------------- 420 */ 421#define CONFIG_SYS_RCCR 0 422 423/* 424 * Init Memory Controller: 425 * 426 * Bank Bus Machine PortSz Device 427 * ---- --- ------- ------ ------ 428 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) 429 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) 430 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) 431 * 3 unused 432 * 4 60x GPCM 8 bit Board Regs, LEDs, switches 433 * 5 unused 434 * 6 unused 435 * 7 unused 436 * 8 PCMCIA 437 * 9 unused 438 * 10 unused 439 * 11 unused 440*/ 441 442/* Bank 0 - FLASH 443 * 444 */ 445#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ 446 BRx_PS_64 |\ 447 BRx_DECC_NONE |\ 448 BRx_MS_GPCM_P |\ 449 BRx_V) 450 451#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ 452 ORxG_CSNT |\ 453 ORxG_ACS_DIV1 |\ 454 ORxG_SCY_6_CLK |\ 455 ORxG_EHTR) 456 457/* Bank 1 - SDRAM 458 * 459 */ 460#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ 461 BRx_PS_64 |\ 462 BRx_MS_SDRAM_P |\ 463 BRx_V) 464 465#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ 466 ORxS_BPD_4 |\ 467 ORxS_ROWST_PBI0_A8 |\ 468 ORxS_NUMR_12 |\ 469 ORxS_IBID) 470 471#define CONFIG_SYS_PSDMR 0x014DA412 472#define CONFIG_SYS_PSRT 0x79 473 474 475/* Bank 2 - SDRAM 476 * 477 */ 478#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ 479 BRx_PS_32 |\ 480 BRx_MS_SDRAM_L |\ 481 BRx_V) 482 483#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ 484 ORxS_BPD_4 |\ 485 ORxS_ROWST_PBI0_A9 |\ 486 ORxS_NUMR_12) 487 488#define CONFIG_SYS_LSDMR 0x0169A512 489#define CONFIG_SYS_LSRT 0x79 490 491#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK) 492 493/* Bank 4 - On board registers 494 * 495 */ 496#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ 497 BRx_PS_8 |\ 498 BRx_MS_GPCM_P |\ 499 BRx_V) 500 501#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ 502 ORxG_CSNT |\ 503 ORxG_ACS_DIV1 |\ 504 ORxG_SCY_5_CLK |\ 505 ORxG_TRLX) 506 507#endif /* __CONFIG_H */ 508