1/* 2 * (C) Copyright 2002 3 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG 4 * 5 * This file is based on similar values for other boards found in other 6 * U-Boot config files, and some that I found in the EP8260 manual. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27/* 28 * board/config.h - configuration options, board specific 29 * 30 * "EP8260 H, V.1.1" 31 * - 64M 60x Bus SDRAM 32 * - 32M Local Bus SDRAM 33 * - 16M Flash (4 x AM29DL323DB90WDI) 34 * - 128k NVRAM with RTC 35 * 36 * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2) 37 * - 300MHz/133MHz/66MHz 38 * - 64M 60x Bus SDRAM 39 * - 32M Local Bus SDRAM 40 * - 32M Flash 41 * - 128k NVRAM with RTC 42 */ 43 44#ifndef __CONFIG_H 45#define __CONFIG_H 46 47/* Define this to enable support the EP8260 H2 version */ 48#define CONFIG_SYS_EP8260_H2 1 49/* #undef CONFIG_SYS_EP8260_H2 */ 50 51#define CONFIG_SYS_TEXT_BASE 0xFFF00000 52 53#define CONFIG_CPM2 1 /* Has a CPM2 */ 54 55/* What is the oscillator's (UX2) frequency in Hz? */ 56#define CONFIG_8260_CLKIN (66 * 1000 * 1000) 57 58/*----------------------------------------------------------------------- 59 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual 60 *----------------------------------------------------------------------- 61 * What should MODCK_H be? It is dependent on the oscillator 62 * frequency, MODCK[1-3], and desired CPM and core frequencies. 63 * Here are some example values (all frequencies are in MHz): 64 * 65 * MODCK_H MODCK[1-3] Osc CPM Core 66 * ------- ---------- --- --- ---- 67 * 0x2 0x2 33 133 133 68 * 0x2 0x3 33 133 166 69 * 0x2 0x4 33 133 200 70 * 0x2 0x5 33 133 233 71 * 0x2 0x6 33 133 266 72 * 73 * 0x5 0x5 66 133 133 74 * 0x5 0x6 66 133 166 75 * 0x5 0x7 66 133 200 * 76 * 0x6 0x0 66 133 233 77 * 0x6 0x1 66 133 266 78 * 0x6 0x2 66 133 300 79 */ 80#ifdef CONFIG_SYS_EP8260_H2 81#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) 82#else 83#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) 84#endif 85 86/* Define this if you want to boot from 0x00000100. If you don't define 87 * this, you will need to program the bootloader to 0xfff00000, and 88 * get the hardware reset config words at 0xfe000000. The simplest 89 * way to do that is to program the bootloader at both addresses. 90 * It is suggested that you just let U-Boot live at 0x00000000. 91 */ 92/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */ 93/* #undef CONFIG_SYS_SBC_BOOT_LOW */ 94 95/* The reset command will not work as expected if the reset address does 96 * not point to the correct address. 97 */ 98 99#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 100 101/* What should the base address of the main FLASH be and how big is 102 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk 103 * The main FLASH is whichever is connected to *CS0. U-Boot expects 104 * this to be the SIMM. 105 */ 106#ifdef CONFIG_SYS_EP8260_H2 107#define CONFIG_SYS_FLASH0_BASE 0xFE000000 108#define CONFIG_SYS_FLASH0_SIZE 32 109#else 110#define CONFIG_SYS_FLASH0_BASE 0xFF000000 111#define CONFIG_SYS_FLASH0_SIZE 16 112#endif 113 114/* What should the base address of the secondary FLASH be and how big 115 * is it (in Mbytes)? The secondary FLASH is whichever is connected 116 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't 117 * want it enabled, don't define these constants. 118 */ 119#define CONFIG_SYS_FLASH1_BASE 0 120#define CONFIG_SYS_FLASH1_SIZE 0 121#undef CONFIG_SYS_FLASH1_BASE 122#undef CONFIG_SYS_FLASH1_SIZE 123 124/* What should be the base address of SDRAM DIMM (60x bus) and how big is 125 * it (in Mbytes)? 126*/ 127#define CONFIG_SYS_SDRAM0_BASE 0x00000000 128#define CONFIG_SYS_SDRAM0_SIZE 64 129 130/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the 131 * local bus (8260 local bus is NOT cacheable!) 132*/ 133/* #define CONFIG_SYS_LSDRAM */ 134#undef CONFIG_SYS_LSDRAM 135 136#ifdef CONFIG_SYS_LSDRAM 137/* What should be the base address of SDRAM DIMM (local bus) and how big is 138 * it (in Mbytes)? 139*/ 140 #define CONFIG_SYS_SDRAM1_BASE 0x04000000 141 #define CONFIG_SYS_SDRAM1_SIZE 32 142#else 143 #define CONFIG_SYS_SDRAM1_BASE 0 144 #define CONFIG_SYS_SDRAM1_SIZE 0 145 #undef CONFIG_SYS_SDRAM1_BASE 146 #undef CONFIG_SYS_SDRAM1_SIZE 147#endif /* CONFIG_SYS_LSDRAM */ 148 149/* What should be the base address of NVRAM and how big is 150 * it (in Bytes) 151 */ 152#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 153#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 154 155/* The RTC is a Dallas DS1556 156 */ 157#define CONFIG_RTC_DS1556 158 159/* What should be the base address of the LEDs and switch S0? 160 * If you don't want them enabled, don't define this. 161 */ 162#define CONFIG_SYS_LED_BASE 0x00000000 163#undef CONFIG_SYS_LED_BASE 164 165/* 166 * select serial console configuration 167 * 168 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 169 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 170 * for SCC). 171 * 172 * if CONFIG_CONS_NONE is defined, then the serial console routines must 173 * defined elsewhere. 174 */ 175#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 176#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 177#undef CONFIG_CONS_NONE /* define if console on neither */ 178#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ 179 180/* 181 * select ethernet configuration 182 * 183 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 184 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 185 * for FCC) 186 * 187 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 188 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 189 */ 190#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ 191#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ 192#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ 193#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ 194 195#if ( CONFIG_ETHER_INDEX == 3 ) 196 197/* 198 * - Rx-CLK is CLK15 199 * - Tx-CLK is CLK16 200 * - RAM for BD/Buffers is on the local Bus (see 28-13) 201 * - Enable Half Duplex in FSMR 202 */ 203# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) 204# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) 205 206/* 207 * - RAM for BD/Buffers is on the local Bus (see 28-13) 208 */ 209#ifdef CONFIG_SYS_LSDRAM 210 #define CONFIG_SYS_CPMFCR_RAMTYPE 3 211#else /* CONFIG_SYS_LSDRAM */ 212 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 213#endif /* CONFIG_SYS_LSDRAM */ 214 215/* - Enable Half Duplex in FSMR */ 216/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ 217# define CONFIG_SYS_FCC_PSMR 0 218 219#else /* CONFIG_ETHER_INDEX */ 220# error "on EP8260 ethernet must be FCC3" 221#endif /* CONFIG_ETHER_INDEX */ 222 223/* 224 * select i2c support configuration 225 * 226 * Supported configurations are {none, software, hardware} drivers. 227 * If the software driver is chosen, there are some additional 228 * configuration items that the driver uses to drive the port pins. 229 */ 230#undef CONFIG_HARD_I2C /* I2C with hardware support */ 231#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 232#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 233#define CONFIG_SYS_I2C_SLAVE 0x7F 234 235/* 236 * Software (bit-bang) I2C driver configuration 237 */ 238#ifdef CONFIG_SOFT_I2C 239#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 240#define I2C_ACTIVE (iop->pdir |= 0x00010000) 241#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 242#define I2C_READ ((iop->pdat & 0x00010000) != 0) 243#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 244 else iop->pdat &= ~0x00010000 245#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 246 else iop->pdat &= ~0x00020000 247#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 248#endif /* CONFIG_SOFT_I2C */ 249 250/* #define CONFIG_RTC_DS174x */ 251 252/* Define this to reserve an entire FLASH sector (256 KB) for 253 * environment variables. Otherwise, the environment will be 254 * put in the same sector as U-Boot, and changing variables 255 * will erase U-Boot temporarily 256 */ 257#define CONFIG_ENV_IN_OWN_SECT 258 259/* Define to allow the user to overwrite serial and ethaddr */ 260#define CONFIG_ENV_OVERWRITE 261 262/* What should the console's baud rate be? */ 263#ifdef CONFIG_SYS_EP8260_H2 264#define CONFIG_BAUDRATE 9600 265#else 266#define CONFIG_BAUDRATE 115200 267#endif 268 269/* Ethernet MAC address */ 270#define CONFIG_ETHADDR 00:10:EC:00:30:8C 271 272#define CONFIG_IPADDR 192.168.254.130 273#define CONFIG_SERVERIP 192.168.254.49 274 275/* Set to a positive value to delay for running BOOTCOMMAND */ 276#define CONFIG_BOOTDELAY -1 277 278/* undef this to save memory */ 279#define CONFIG_SYS_LONGHELP 280 281/* Monitor Command Prompt */ 282#define CONFIG_SYS_PROMPT "=> " 283 284/* Define this variable to enable the "hush" shell (from 285 Busybox) as command line interpreter, thus enabling 286 powerful command line syntax like 287 if...then...else...fi conditionals or `&&' and '||' 288 constructs ("shell scripts"). 289 If undefined, you get the old, much simpler behaviour 290 with a somewhat smapper memory footprint. 291*/ 292#define CONFIG_SYS_HUSH_PARSER 293#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 294 295 296/* 297 * BOOTP options 298 */ 299#define CONFIG_BOOTP_BOOTFILESIZE 300#define CONFIG_BOOTP_BOOTPATH 301#define CONFIG_BOOTP_GATEWAY 302#define CONFIG_BOOTP_HOSTNAME 303 304 305/* 306 * Command line configuration. 307 */ 308#include <config_cmd_default.h> 309 310#define CONFIG_CMD_ASKENV 311#define CONFIG_CMD_BEDBUG 312#define CONFIG_CMD_CACHE 313#define CONFIG_CMD_CDP 314#define CONFIG_CMD_DATE 315#define CONFIG_CMD_DIAG 316#define CONFIG_CMD_ELF 317#define CONFIG_CMD_FAT 318#define CONFIG_CMD_I2C 319#define CONFIG_CMD_IMMAP 320#define CONFIG_CMD_IRQ 321#define CONFIG_CMD_PING 322#define CONFIG_CMD_PORTIO 323#define CONFIG_CMD_REGINFO 324#define CONFIG_CMD_SAVES 325#define CONFIG_CMD_SDRAM 326#define CONFIG_CMD_SNTP 327 328#undef CONFIG_CMD_DCR 329#undef CONFIG_CMD_XIMG 330 331/* Where do the internal registers live? */ 332#define CONFIG_SYS_IMMR 0xF0000000 333#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 334 335/* Where do the on board registers (CS4) live? */ 336#define CONFIG_SYS_REGS_BASE 0xFA000000 337 338/***************************************************************************** 339 * 340 * You should not have to modify any of the following settings 341 * 342 *****************************************************************************/ 343 344#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 345#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ 346 347#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 348 349/* 350 * Miscellaneous configurable options 351 */ 352#if defined(CONFIG_CMD_KGDB) 353# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 354#else 355# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 356#endif 357 358/* Print Buffer Size */ 359#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 360 361#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ 362 363#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 364 365#ifdef CONFIG_SYS_LSDRAM 366 #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ 367 #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ 368#else 369 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 370 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ 371#endif /* CONFIG_SYS_LSDRAM */ 372 373#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 374 375#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 376#define CONFIG_SYS_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */ 377 378#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 379 380/* valid baudrates */ 381#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 382 383/* 384 * Low Level Configuration Settings 385 * (address mappings, register initial values, etc.) 386 * You should know what you are doing if you make changes here. 387 */ 388 389#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 390#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE 391 392/*----------------------------------------------------------------------- 393 * Hard Reset Configuration Words 394 */ 395 396#if defined(CONFIG_SYS_SBC_BOOT_LOW) 397# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) 398#else 399# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000) 400#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ 401 402#ifdef CONFIG_SYS_EP8260_H2 403/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */ 404#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\ 405 ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\ 406 ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) ) 407 408#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\ 409 HRCW_L2CPC01 |\ 410 CONFIG_SYS_SBC_HRCW_IMMR |\ 411 HRCW_APPC10 |\ 412 HRCW_CS10PC01 |\ 413 CONFIG_SYS_SBC_MODCK_H |\ 414 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) 415#else 416#define CONFIG_SYS_HRCW_MASTER 0x10400245 417#endif 418 419/* no slaves */ 420#define CONFIG_SYS_HRCW_SLAVE1 0 421#define CONFIG_SYS_HRCW_SLAVE2 0 422#define CONFIG_SYS_HRCW_SLAVE3 0 423#define CONFIG_SYS_HRCW_SLAVE4 0 424#define CONFIG_SYS_HRCW_SLAVE5 0 425#define CONFIG_SYS_HRCW_SLAVE6 0 426#define CONFIG_SYS_HRCW_SLAVE7 0 427 428/*----------------------------------------------------------------------- 429 * Definitions for initial stack pointer and data area (in DPRAM) 430 */ 431#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 432#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 433#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 434#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 435 436/*----------------------------------------------------------------------- 437 * Start addresses for the final memory configuration 438 * (Set up by the startup code) 439 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 440 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. 441 */ 442#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 443 444 445#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 446# define CONFIG_SYS_RAMBOOT 447#endif 448 449#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 450#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 451 452/* 453 * For booting Linux, the board info and command line data 454 * have to be in the first 8 MB of memory, since this is 455 * the maximum mapped by the Linux kernel during initialization. 456 */ 457#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 458 459/*----------------------------------------------------------------------- 460 * FLASH and environment organization 461 */ 462#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 463#ifdef CONFIG_SYS_EP8260_H2 464#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 465#else 466#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 467#endif 468 469#ifdef CONFIG_SYS_EP8260_H2 470#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ 471#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 472#else 473#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ 474#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ 475#endif 476 477#ifndef CONFIG_SYS_RAMBOOT 478# define CONFIG_ENV_IS_IN_FLASH 1 479 480# ifdef CONFIG_ENV_IN_OWN_SECT 481# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 482# define CONFIG_ENV_SECT_SIZE 0x40000 483# else 484# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) 485# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 486# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ 487# endif /* CONFIG_ENV_IN_OWN_SECT */ 488#else 489# define CONFIG_ENV_IS_IN_NVRAM 1 490# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 491# define CONFIG_ENV_SIZE 0x200 492#endif /* CONFIG_SYS_RAMBOOT */ 493 494/*----------------------------------------------------------------------- 495 * Cache Configuration 496 */ 497#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 498 499#if defined(CONFIG_CMD_KGDB) 500# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 501#endif 502 503/*----------------------------------------------------------------------- 504 * HIDx - Hardware Implementation-dependent Registers 2-11 505 *----------------------------------------------------------------------- 506 * HID0 also contains cache control - initially enable both caches and 507 * invalidate contents, then the final state leaves only the instruction 508 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 509 * but Soft reset does not. 510 * 511 * HID1 has only read-only information - nothing to set. 512 */ 513#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ 514 HID0_DCE |\ 515 HID0_ICFI |\ 516 HID0_DCI |\ 517 HID0_IFEM |\ 518 HID0_ABE) 519#ifdef CONFIG_SYS_LSDRAM 520/* 8260 local bus is NOT cacheable */ 521#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ 522 HID0_IFEM |\ 523 HID0_ABE |\ 524 HID0_EMCP) 525#else /* !CONFIG_SYS_LSDRAM */ 526#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ 527 HID0_IFEM |\ 528 HID0_ABE |\ 529 HID0_EMCP) 530#endif /* CONFIG_SYS_LSDRAM */ 531 532#define CONFIG_SYS_HID2 0 533 534/*----------------------------------------------------------------------- 535 * RMR - Reset Mode Register 536 *----------------------------------------------------------------------- 537 */ 538#define CONFIG_SYS_RMR 0 539 540/*----------------------------------------------------------------------- 541 * BCR - Bus Configuration 4-25 542 *----------------------------------------------------------------------- 543 */ 544#define CONFIG_SYS_BCR (BCR_EBM |\ 545 BCR_PLDP |\ 546 BCR_EAV |\ 547 BCR_NPQM0) 548 549/*----------------------------------------------------------------------- 550 * SIUMCR - SIU Module Configuration 4-31 551 *----------------------------------------------------------------------- 552 */ 553#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ 554 SIUMCR_APPC10 |\ 555 SIUMCR_CS10PC01) 556 557/*----------------------------------------------------------------------- 558 * SYPCR - System Protection Control 11-9 559 * SYPCR can only be written once after reset! 560 *----------------------------------------------------------------------- 561 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 562 */ 563#ifdef CONFIG_SYS_EP8260_H2 564/* TBD: Find out why setting the BMT to 0xff causes the FCC to 565 * generate TX buffer underrun errors for large packets under 566 * Linux 567 */ 568#define CONFIG_SYS_SYPCR_BMT 0x00000600 569#else 570#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT 571#endif 572 573#ifdef CONFIG_SYS_LSDRAM 574#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ 575 CONFIG_SYS_SYPCR_BMT |\ 576 SYPCR_PBME |\ 577 SYPCR_LBME |\ 578 SYPCR_SWP) 579#else 580#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ 581 CONFIG_SYS_SYPCR_BMT |\ 582 SYPCR_PBME |\ 583 SYPCR_SWP) 584#endif 585 586/*----------------------------------------------------------------------- 587 * TMCNTSC - Time Counter Status and Control 4-40 588 *----------------------------------------------------------------------- 589 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 590 * and enable Time Counter 591 */ 592#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ 593 TMCNTSC_ALR |\ 594 TMCNTSC_TCF |\ 595 TMCNTSC_TCE) 596 597/*----------------------------------------------------------------------- 598 * PISCR - Periodic Interrupt Status and Control 4-42 599 *----------------------------------------------------------------------- 600 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 601 * Periodic timer 602 */ 603#ifdef CONFIG_SYS_EP8260_H2 604#define CONFIG_SYS_PISCR (PISCR_PS |\ 605 PISCR_PTF |\ 606 PISCR_PTE) 607#else 608#define CONFIG_SYS_PISCR 0 609#endif 610 611/*----------------------------------------------------------------------- 612 * SCCR - System Clock Control 9-8 613 *----------------------------------------------------------------------- 614 */ 615#ifdef CONFIG_SYS_EP8260_H2 616#define CONFIG_SYS_SCCR (SCCR_DFBRG00) 617#else 618#define CONFIG_SYS_SCCR (SCCR_DFBRG01) 619#endif 620 621/*----------------------------------------------------------------------- 622 * RCCR - RISC Controller Configuration 13-7 623 *----------------------------------------------------------------------- 624 */ 625#define CONFIG_SYS_RCCR 0 626 627/*----------------------------------------------------------------------- 628 * MPTPR - Memory Refresh Timer Prescale Register 10-32 629 *----------------------------------------------------------------------- 630 */ 631#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK) 632 633/* 634 * Init Memory Controller: 635 * 636 * Bank Bus Machine PortSz Device 637 * ---- --- ------- ------ ------ 638 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) 639 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) 640 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) 641 * 3 unused 642 * 4 60x GPCM 8 bit Board Regs, NVRTC 643 * 5 unused 644 * 6 unused 645 * 7 unused 646 * 8 PCMCIA 647 * 9 unused 648 * 10 unused 649 * 11 unused 650*/ 651 652/*----------------------------------------------------------------------- 653 * BRx - Base Register 654 * Ref: Section 10.3.1 on page 10-14 655 * ORx - Option Register 656 * Ref: Section 10.3.2 on page 10-18 657 *----------------------------------------------------------------------- 658 */ 659 660/* Bank 0 - FLASH 661 * 662 */ 663#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ 664 BRx_PS_64 |\ 665 BRx_DECC_NONE |\ 666 BRx_MS_GPCM_P |\ 667 BRx_V) 668 669#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ 670 ORxG_CSNT |\ 671 ORxG_ACS_DIV1 |\ 672 ORxG_SCY_8_CLK |\ 673 ORxG_EHTR) 674 675/* Bank 1 - SDRAM 676 * PSDRAM 677 */ 678#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ 679 BRx_PS_64 |\ 680 BRx_MS_SDRAM_P |\ 681 BRx_V) 682 683#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ 684 ORxS_BPD_4 |\ 685 ORxS_ROWST_PBI1_A6 |\ 686 ORxS_NUMR_12) 687 688#ifdef CONFIG_SYS_EP8260_H2 689#define CONFIG_SYS_PSDMR 0xC34E246E 690#else 691#define CONFIG_SYS_PSDMR 0xC34E2462 692#endif 693 694#define CONFIG_SYS_PSRT 0x64 695 696#ifdef CONFIG_SYS_LSDRAM 697/* Bank 2 - SDRAM 698 * LSDRAM 699 */ 700 701 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ 702 BRx_PS_32 |\ 703 BRx_MS_SDRAM_L |\ 704 BRx_V) 705 706 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ 707 ORxS_BPD_4 |\ 708 ORxS_ROWST_PBI0_A9 |\ 709 ORxS_NUMR_12) 710 711 #define CONFIG_SYS_LSDMR 0x416A2562 712 #define CONFIG_SYS_LSRT 0x64 713#else 714 #define CONFIG_SYS_LSRT 0x0 715#endif /* CONFIG_SYS_LSDRAM */ 716 717/* Bank 4 - On board registers 718 * NVRTC and BCSR 719 */ 720#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ 721 BRx_PS_8 |\ 722 BRx_MS_GPCM_P |\ 723 BRx_V) 724/* 725#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ 726 ORxG_CSNT |\ 727 ORxG_ACS_DIV1 |\ 728 ORxG_SCY_10_CLK |\ 729 ORxG_TRLX) 730*/ 731#define CONFIG_SYS_OR4_PRELIM 0xfff00854 732 733#ifdef _NOT_USED_SINCE_NOT_WORKING_ 734/* Bank 8 - On board registers 735 * PCMCIA (currently not working!) 736 */ 737#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ 738 BRx_PS_16 |\ 739 BRx_MS_GPCM_P |\ 740 BRx_V) 741 742#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\ 743 ORxG_CSNT |\ 744 ORxG_ACS_DIV1 |\ 745 ORxG_SETA |\ 746 ORxG_SCY_10_CLK) 747#endif 748 749/* 750 * JFFS2 partitions 751 * 752 */ 753/* No command line, one static partition, whole device */ 754#undef CONFIG_CMD_MTDPARTS 755#define CONFIG_JFFS2_DEV "nor0" 756#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 757#define CONFIG_JFFS2_PART_OFFSET 0x00000000 758 759/* mtdparts command line support */ 760/* Note: fake mtd_id used, no linux mtd map file */ 761/* 762#define CONFIG_CMD_MTDPARTS 763#define MTDIDS_DEFAULT "" 764#define MTDPARTS_DEFAULT "" 765*/ 766 767#endif /* __CONFIG_H */ 768