1/* 2 * Copyright (C) 2006 Embedded Planet, LLC. 3 * 4 * U-Boot configuration for Embedded Planet EP82xxM boards. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25#ifndef __CONFIG_H 26#define __CONFIG_H 27 28#define CONFIG_MPC8260 29#define CPU_ID_STR "MPC8270" 30 31#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ 32 /* 256MB SDRAM / 64MB FLASH */ 33 34#define CONFIG_SYS_TEXT_BASE 0xFFF00000 35 36#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 37 38/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ 39#define CONFIG_ENV_OVERWRITE 40 41/* 42 * Select serial console configuration 43 * 44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 46 * for SCC). 47 */ 48#define CONFIG_CONS_ON_SMC /* Console is on SMC */ 49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 50#undef CONFIG_CONS_NONE /* It's not on external UART */ 51#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ 52 53#define CONFIG_SYS_BCSR 0xFA000000 54 55/* 56 * Select ethernet configuration 57 * 58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 60 * SCC, 1-3 for FCC) 61 * 62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 63 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 64 * must be unset. 65 */ 66#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ 67#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ 68#undef CONFIG_ETHER_NONE /* No external Ethernet */ 69 70#define CONFIG_NET_MULTI 71 72#define CONFIG_ETHER_ON_FCC2 73#define CONFIG_ETHER_ON_FCC3 74 75#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) 76#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) 77#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 78#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 79 80#define CONFIG_SYS_CPMFCR_RAMTYPE 0 81#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 82 83#define CONFIG_MII /* MII PHY management */ 84#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ 85 86/* 87 * GPIO pins used for bit-banged MII communications 88 */ 89#define MDIO_PORT 0 /* Not used - implemented in BCSR */ 90 91#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) 92#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) 93#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) 94 95#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \ 96 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE 97 98#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \ 99 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD 100 101#define MIIDELAY udelay(1) 102 103 104#ifndef CONFIG_8260_CLKIN 105#define CONFIG_8260_CLKIN 66000000 /* in Hz */ 106#endif 107 108#define CONFIG_BAUDRATE 115200 109 110#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ 111 112 113/* 114 * BOOTP options 115 */ 116#define CONFIG_BOOTP_BOOTFILESIZE 117#define CONFIG_BOOTP_BOOTPATH 118#define CONFIG_BOOTP_GATEWAY 119#define CONFIG_BOOTP_HOSTNAME 120 121 122/* 123 * Command line configuration. 124 */ 125#include <config_cmd_default.h> 126 127 128#define CONFIG_CMD_DHCP 129#define CONFIG_CMD_ECHO 130#define CONFIG_CMD_I2C 131#define CONFIG_CMD_IMMAP 132#define CONFIG_CMD_MII 133#define CONFIG_CMD_PING 134#define CONFIG_CMD_DATE 135#define CONFIG_CMD_DTT 136#define CONFIG_CMD_EEPROM 137#define CONFIG_CMD_PCI 138#define CONFIG_CMD_DIAG 139 140 141#define CONFIG_ETHADDR 00:10:EC:00:88:65 142#define CONFIG_HAS_ETH1 143#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 144#define CONFIG_IPADDR 10.0.0.245 145#define CONFIG_HOSTNAME EP82xxM 146#define CONFIG_SERVERIP 10.0.0.26 147#define CONFIG_GATEWAYIP 10.0.0.1 148#define CONFIG_NETMASK 255.255.255.0 149#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 150#define CONFIG_ENV_IN_OWN_SECT 1 151#define CONFIG_AUTO_COMPLETE 1 152#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3" 153 154#if defined(CONFIG_CMD_KGDB) 155#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 156#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 157#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 158#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ 159#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 160#endif 161 162#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ 163#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 164 165/* 166 * Miscellaneous configurable options 167 */ 168#define CONFIG_SYS_HUSH_PARSER 169#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 170#define CONFIG_SYS_LONGHELP /* undef to save memory */ 171#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ 172#if defined(CONFIG_CMD_KGDB) 173#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 174#else 175#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 176#endif 177#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 178#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 179#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 180 181#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 182#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 183 184#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 185 186#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 187 188#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 189 190/*----------------------------------------------------------------------- 191 * Environment 192 *----------------------------------------------------------------------*/ 193/* 194 * Define here the location of the environment variables (FLASH or EEPROM). 195 * Note: DENX encourages to use redundant environment in FLASH. 196 */ 197#if 1 198#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 199#else 200#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 201#endif 202 203/*----------------------------------------------------------------------- 204 * FLASH related 205 *----------------------------------------------------------------------*/ 206#define CONFIG_SYS_FLASH_BASE 0xFC000000 207#define CONFIG_SYS_FLASH_CFI 208#define CONFIG_FLASH_CFI_DRIVER 209#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 210#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 211#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ 212 213#ifdef CONFIG_ENV_IS_IN_FLASH 214#define CONFIG_ENV_SECT_SIZE 0x20000 215#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 216#endif /* CONFIG_ENV_IS_IN_FLASH */ 217 218/*----------------------------------------------------------------------- 219 * I2C 220 *----------------------------------------------------------------------*/ 221/* EEPROM Configuration */ 222#define CONFIG_SYS_EEPROM_SIZE 0x1000 223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 224#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 225#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 226#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 227 228#ifdef CONFIG_ENV_IS_IN_EEPROM 229#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ 230#define CONFIG_ENV_OFFSET 0x0 231#endif /* CONFIG_ENV_IS_IN_EEPROM */ 232 233/* RTC Configuration */ 234#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ 235#define CONFIG_SYS_I2C_RTC_ADDR 0x68 236#define CONFIG_M41T11_BASE_YEAR 1900 237 238/* I2C SYSMON (LM75) */ 239#define CONFIG_DTT_LM75 1 240#define CONFIG_DTT_SENSORS {0} 241#define CONFIG_SYS_DTT_MAX_TEMP 70 242#define CONFIG_SYS_DTT_LOW_TEMP -30 243#define CONFIG_SYS_DTT_HYSTERESIS 3 244 245/*----------------------------------------------------------------------- 246 * NVRAM Configuration 247 *----------------------------------------------------------------------- 248 */ 249#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 250#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 251 252 253/*----------------------------------------------------------------------- 254 * PCI stuff 255 *----------------------------------------------------------------------- 256 */ 257/* General PCI */ 258#define CONFIG_PCI /* include pci support */ 259#define CONFIG_PCI_PNP /* do pci plug-and-play */ 260#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 261#define CONFIG_PCI_BOOTDELAY 0 262 263/* PCI Memory map (if different from default map */ 264#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ 265#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 266#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ 267 PICMR_PREFETCH_EN) 268 269/* 270 * These are the windows that allow the CPU to access PCI address space. 271 * All three PCI master windows, which allow the CPU to access PCI 272 * prefetch, non prefetch, and IO space (see below), must all fit within 273 * these windows. 274 */ 275 276/* 277 * Master window that allows the CPU to access PCI Memory (prefetch). 278 * This window will be setup with the second set of Outbound ATU registers 279 * in the bridge. 280 */ 281 282#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 283#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ 284#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL 285#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ 286#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) 287 288/* 289 * Master window that allows the CPU to access PCI Memory (non-prefetch). 290 * This window will be setup with the second set of Outbound ATU registers 291 * in the bridge. 292 */ 293 294#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ 295#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ 296#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 297#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ 298#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) 299 300/* 301 * Master window that allows the CPU to access PCI IO space. 302 * This window will be setup with the first set of Outbound ATU registers 303 * in the bridge. 304 */ 305 306#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ 307#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ 308#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 309#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ 310#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) 311 312 313/* PCIBR0 - for PCI IO*/ 314#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ 315#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ 316/* PCIBR1 - prefetch and non-prefetch regions joined together */ 317#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL 318#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) 319 320 321#define CONFIG_SYS_DIRECT_FLASH_TFTP 322 323#if defined(CONFIG_CMD_JFFS2) 324#define CONFIG_SYS_JFFS2_FIRST_BANK 0 325#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS 326#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 327#define CONFIG_SYS_JFFS2_LAST_SECTOR 62 328#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS 329#define CONFIG_SYS_JFFS_CUSTOM_PART 330#endif 331 332#if defined(CONFIG_CMD_I2C) 333#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 334#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 335#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ 336#endif 337 338#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 339#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 340#define CONFIG_SYS_RAMBOOT 341#endif 342 343#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ 344 345#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 346#define CONFIG_SYS_IMMR 0xF0000000 347 348#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 349#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ 350#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 351#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 352 353 354/* Hard reset configuration word */ 355#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ 356/* No slaves */ 357#define CONFIG_SYS_HRCW_SLAVE1 0 358#define CONFIG_SYS_HRCW_SLAVE2 0 359#define CONFIG_SYS_HRCW_SLAVE3 0 360#define CONFIG_SYS_HRCW_SLAVE4 0 361#define CONFIG_SYS_HRCW_SLAVE5 0 362#define CONFIG_SYS_HRCW_SLAVE6 0 363#define CONFIG_SYS_HRCW_SLAVE7 0 364 365#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 366#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 367 368#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 369#if defined(CONFIG_CMD_KGDB) 370#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 371#endif 372 373#define CONFIG_SYS_HID0_INIT 0 374#define CONFIG_SYS_HID0_FINAL 0 375 376#define CONFIG_SYS_HID2 0 377 378#define CONFIG_SYS_SIUMCR 0x02610000 379#define CONFIG_SYS_SYPCR 0xFFFF0689 380#define CONFIG_SYS_BCR 0x8080E000 381#define CONFIG_SYS_SCCR 0x00000001 382 383#define CONFIG_SYS_RMR 0 384#define CONFIG_SYS_TMCNTSC 0x000000C3 385#define CONFIG_SYS_PISCR 0x00000083 386#define CONFIG_SYS_RCCR 0 387 388#define CONFIG_SYS_MPTPR 0x0A00 389#define CONFIG_SYS_PSDMR 0xC432246E 390#define CONFIG_SYS_PSRT 0x32 391 392#define CONFIG_SYS_SDRAM_BASE 0x00000000 393#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) 394#define CONFIG_SYS_SDRAM_OR 0xF0002900 395 396#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) 397#define CONFIG_SYS_OR0_PRELIM 0xFC000882 398#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001) 399#define CONFIG_SYS_OR4_PRELIM 0xFFF00050 400 401#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 402 403#endif /* __CONFIG_H */ 404