1/* 2 * Copyright (C) 2008 Atmel Corporation 3 * 4 * Configuration settings for the Favr-32 EarthLCD LCD kit. 5 * 6 * See file CREDITS for list of people who contributed to this project. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 20 * Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22#ifndef __CONFIG_H 23#define __CONFIG_H 24 25#include <asm/arch/memory-map.h> 26 27#define CONFIG_AVR32 1 28#define CONFIG_AT32AP 1 29#define CONFIG_AT32AP7000 1 30#define CONFIG_FAVR32_EZKIT 1 31 32#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1 33 34/* 35 * Timer clock frequency. We're using the CPU-internal COUNT register 36 * for this, so this is equivalent to the CPU core clock frequency 37 */ 38#define CONFIG_SYS_HZ 1000 39 40/* 41 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 42 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the 43 * PLL frequency. 44 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz 45 */ 46#define CONFIG_PLL 1 47#define CONFIG_SYS_POWER_MANAGER 1 48#define CONFIG_SYS_OSC0_HZ 20000000 49#define CONFIG_SYS_PLL0_DIV 1 50#define CONFIG_SYS_PLL0_MUL 7 51#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 52/* 53 * Set the CPU running at: 54 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz 55 */ 56#define CONFIG_SYS_CLKDIV_CPU 0 57/* 58 * Set the HSB running at: 59 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz 60 */ 61#define CONFIG_SYS_CLKDIV_HSB 1 62/* 63 * Set the PBA running at: 64 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz 65 */ 66#define CONFIG_SYS_CLKDIV_PBA 2 67/* 68 * Set the PBB running at: 69 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz 70 */ 71#define CONFIG_SYS_CLKDIV_PBB 1 72 73/* Reserve VM regions for SDRAM and NOR flash */ 74#define CONFIG_SYS_NR_VM_REGIONS 2 75 76/* 77 * The PLLOPT register controls the PLL like this: 78 * icp = PLLOPT<2> 79 * ivco = PLLOPT<1:0> 80 * 81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 82 */ 83#define CONFIG_SYS_PLL0_OPT 0x04 84 85#undef CONFIG_USART0 86#undef CONFIG_USART1 87#undef CONFIG_USART2 88#define CONFIG_USART3 1 89 90/* User serviceable stuff */ 91#define CONFIG_DOS_PARTITION 1 92 93#define CONFIG_CMDLINE_TAG 1 94#define CONFIG_SETUP_MEMORY_TAGS 1 95#define CONFIG_INITRD_TAG 1 96 97#define CONFIG_STACKSIZE (2048) 98 99#define CONFIG_BAUDRATE 115200 100#define CONFIG_BOOTARGS \ 101 "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" 102 103#define CONFIG_BOOTCOMMAND \ 104 "fsload; bootm $(fileaddr)" 105 106/* 107 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage 108 * data on the serial line may interrupt the boot sequence. 109 */ 110#define CONFIG_BOOTDELAY 1 111#define CONFIG_AUTOBOOT 1 112#define CONFIG_AUTOBOOT_KEYED 1 113#define CONFIG_AUTOBOOT_PROMPT \ 114 "Press SPACE to abort autoboot in %d seconds\n", bootdelay 115#define CONFIG_AUTOBOOT_DELAY_STR "d" 116#define CONFIG_AUTOBOOT_STOP_STR " " 117 118/* 119 * After booting the board for the first time, new ethernet addresses 120 * should be generated and assigned to the environment variables 121 * "ethaddr" and "eth1addr". This is normally done during production. 122 */ 123#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 124#define CONFIG_NET_MULTI 1 125 126/* 127 * BOOTP options 128 */ 129#define CONFIG_BOOTP_SUBNETMASK 130#define CONFIG_BOOTP_GATEWAY 131 132 133/* 134 * Command line configuration. 135 */ 136#include <config_cmd_default.h> 137 138#define CONFIG_CMD_ASKENV 139#define CONFIG_CMD_DHCP 140#define CONFIG_CMD_EXT2 141#define CONFIG_CMD_FAT 142#define CONFIG_CMD_JFFS2 143#define CONFIG_CMD_MMC 144 145#undef CONFIG_CMD_FPGA 146#undef CONFIG_CMD_SETGETDCR 147#undef CONFIG_CMD_SOURCE 148#undef CONFIG_CMD_XIMG 149 150#define CONFIG_ATMEL_USART 1 151#define CONFIG_MACB 1 152#define CONFIG_PORTMUX_PIO 1 153#define CONFIG_SYS_NR_PIOS 5 154#define CONFIG_SYS_HSDRAMC 1 155#define CONFIG_MMC 1 156#define CONFIG_ATMEL_MCI 1 157 158#define CONFIG_SYS_DCACHE_LINESZ 32 159#define CONFIG_SYS_ICACHE_LINESZ 32 160 161#define CONFIG_NR_DRAM_BANKS 1 162 163/* External flash on Favr-32 */ 164#if 0 165#define CONFIG_SYS_FLASH_CFI 1 166#define CONFIG_FLASH_CFI_DRIVER 1 167#endif 168 169#define CONFIG_SYS_FLASH_BASE 0x00000000 170#define CONFIG_SYS_FLASH_SIZE 0x800000 171#define CONFIG_SYS_MAX_FLASH_BANKS 1 172#define CONFIG_SYS_MAX_FLASH_SECT 135 173 174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 175 176#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 177#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 178#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 179 180#define CONFIG_ENV_IS_IN_FLASH 1 181#define CONFIG_ENV_SIZE 65536 182#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 183 184#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 185 186#define CONFIG_SYS_MALLOC_LEN (256*1024) 187#define CONFIG_SYS_DMA_ALLOC_LEN (16384) 188 189/* Allow 4MB for the kernel run-time image */ 190#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 191#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 192 193/* Other configuration settings that shouldn't have to change all that often */ 194#define CONFIG_SYS_PROMPT "U-Boot> " 195#define CONFIG_SYS_CBSIZE 256 196#define CONFIG_SYS_MAXARGS 16 197#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 198#define CONFIG_SYS_LONGHELP 1 199 200#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 201#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) 202#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 203 204#endif /* __CONFIG_H */ 205