LXR uboot/include/configs/utx8245.h

   1/*
   2 * (C) Copyright 2001
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2002
   6 * Gregory E. Allen, gallen@arlut.utexas.edu
   7 * Matthew E. Karger, karger@arlut.utexas.edu
   8 * Applied Research Laboratories, The University of Texas at Austin
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29/*
  30 *
  31 * Configuration settings for the utx8245 board.
  32 *
  33 */
  34
  35/* ------------------------------------------------------------------------- */
  36
  37/*
  38 * board/config.h - configuration options, board specific
  39 */
  40
  41#ifndef __CONFIG_H
  42#define __CONFIG_H
  43
  44/*
  45 * High Level Configuration Options
  46 * (easy to change)
  47 */
  48
  49#define CONFIG_MPC824X          1
  50#define CONFIG_MPC8245          1
  51#define CONFIG_UTX8245          1
  52
  53#define CONFIG_SYS_TEXT_BASE    0xFFF00000
  54
  55#define DEBUG                           1
  56
  57#define CONFIG_IDENT_STRING     " [UTX5] "
  58
  59#define CONFIG_CONS_INDEX       1
  60#define CONFIG_BAUDRATE         57600
  61#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  62
  63#define CONFIG_BOOTDELAY        2
  64#define CONFIG_AUTOBOOT_PROMPT  "autoboot in %d seconds\n", bootdelay
  65#define CONFIG_BOOTCOMMAND      "run nfsboot"   /* autoboot command     */
  66#define CONFIG_BOOTARGS         "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
  67#define CONFIG_ETHADDR          00:AA:00:14:00:05       /* UTX5 */
  68#define CONFIG_SERVERIP         10.8.17.105     /* Spree */
  69#define CONFIG_SYS_TFTP_LOADADDR        10000
  70
  71#define CONFIG_EXTRA_ENV_SETTINGS \
  72        "kernel_addr=FFA00000\0" \
  73        "ramdisk_addr=FF800000\0" \
  74        "u-boot_startaddr=FFB00000\0" \
  75        "u-boot_endaddr=FFB2FFFF\0" \
  76        "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
  77nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
  78        "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
  79        "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
  80        "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
  81        "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
  82        "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  83        "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  84        "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  85        "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
  86${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
  87${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
  88protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  89
  90#define CONFIG_ENV_OVERWRITE
  91
  92
  93/*
  94 * BOOTP options
  95 */
  96#define CONFIG_BOOTP_BOOTFILESIZE
  97#define CONFIG_BOOTP_BOOTPATH
  98#define CONFIG_BOOTP_GATEWAY
  99#define CONFIG_BOOTP_HOSTNAME
 100
 101
 102/*
 103 * Command line configuration.
 104 */
 105#include <config_cmd_default.h>
 106
 107#define CONFIG_CMD_BDI
 108#define CONFIG_CMD_PCI
 109#define CONFIG_CMD_FLASH
 110#define CONFIG_CMD_MEMORY
 111#define CONFIG_CMD_SAVEENV
 112#define CONFIG_CMD_CONSOLE
 113#define CONFIG_CMD_LOADS
 114#define CONFIG_CMD_LOADB
 115#define CONFIG_CMD_IMI
 116#define CONFIG_CMD_CACHE
 117#define CONFIG_CMD_REGINFO
 118#define CONFIG_CMD_NET
 119#define CONFIG_CMD_DHCP
 120#define CONFIG_CMD_I2C
 121#define CONFIG_CMD_DATE
 122
 123
 124/*
 125 * Miscellaneous configurable options
 126 */
 127#define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 128#define CONFIG_SYS_PROMPT       "=> "                   /* Monitor Command Prompt       */
 129#define CONFIG_SYS_CBSIZE       256                             /* Console I/O Buffer Size      */
 130
 131/* Print Buffer Size */
 132#define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 133
 134#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 135#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 136#define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 137
 138
 139/*-----------------------------------------------------------------------
 140 * PCI configuration
 141 *-----------------------------------------------------------------------
 142 */
 143#define CONFIG_PCI                              /* include pci support          */
 144#undef CONFIG_PCI_PNP
 145#define CONFIG_PCI_SCAN_SHOW
 146#define CONFIG_NET_MULTI
 147#define CONFIG_EEPRO100
 148#define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 149#define CONFIG_EEPRO100_SROM_WRITE
 150
 151#define PCI_ENET0_IOADDR        0xF0000000
 152#define PCI_ENET0_MEMADDR       0xF0000000
 153
 154#define PCI_FIREWIRE_IOADDR             0xF1000000
 155#define PCI_FIREWIRE_MEMADDR    0xF1000000
 156/*
 157#define PCI_ENET0_IOADDR        0xFE000000
 158#define PCI_ENET0_MEMADDR       0x80000000
 159
 160#define PCI_FIREWIRE_IOADDR     0x81000000
 161#define PCI_FIREWIRE_MEMADDR    0x81000000
 162*/
 163
 164/*-----------------------------------------------------------------------
 165 * Start addresses for the final memory configuration
 166 * (Set up by the startup code)
 167 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 168 */
 169#define CONFIG_SYS_SDRAM_BASE       0x00000000
 170#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000   /* 256MB  */
 171/*#define CONFIG_SYS_VERY_BIG_RAM       1 */
 172
 173/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
 174 * is actually located at FFF00100.  Therefore, U-Boot is
 175 * physically located at 0xFFB0_0000, but is also mirrored at
 176 * 0xFFF0_0000.
 177 */
 178#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 179
 180#define CONFIG_SYS_EUMB_ADDR        0xFC000000
 181
 182#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 183
 184#define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 185#define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 186
 187/*#define CONFIG_SYS_DRAM_TEST          1 */
 188#define CONFIG_SYS_MEMTEST_START   0x00003000   /* memtest works on     0...256 MB      */
 189#define CONFIG_SYS_MEMTEST_END      0x0ff8ffa7  /* in SDRAM, skips exception */
 190                                                                                /* vectors and U-Boot */
 191
 192
 193/*--------------------------------------------------------------------
 194 * Definitions for initial stack pointer and data area
 195 *------------------------------------------------------------------*/
 196#define CONFIG_SYS_INIT_DATA_SIZE    128        /* Size in bytes reserved for */
 197                                                                        /* initial data */
 198#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 199#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 200#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 201#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 202
 203/*--------------------------------------------------------------------
 204 * NS16550 Configuration
 205 *------------------------------------------------------------------*/
 206#define CONFIG_SYS_NS16550
 207#define CONFIG_SYS_NS16550_SERIAL
 208
 209#define CONFIG_SYS_NS16550_REG_SIZE     1
 210
 211#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
 212#       define CONFIG_SYS_NS16550_CLK           get_bus_freq(0)
 213#else
 214#       define CONFIG_SYS_NS16550_CLK 33000000
 215#endif
 216
 217#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 218#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 219#define CONFIG_SYS_NS16550_COM3 0xFF000000
 220#define CONFIG_SYS_NS16550_COM4 0xFF000008
 221
 222/*--------------------------------------------------------------------
 223 * Low Level Configuration Settings
 224 * (address mappings, register initial values, etc.)
 225 * You should know what you are doing if you make changes here.
 226 * For the detail description refer to the MPC8240 user's manual.
 227 *------------------------------------------------------------------*/
 228
 229#define CONFIG_SYS_CLK_FREQ  33000000
 230#define CONFIG_SYS_HZ                           1000
 231
 232/*#define CONFIG_SYS_ETH_DEV_FN      0x7800 */
 233/*#define CONFIG_SYS_ETH_IOBASE      0x00104000 */
 234
 235/*--------------------------------------------------------------------
 236 * I2C Configuration
 237 *------------------------------------------------------------------*/
 238#if 1
 239#define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 240#undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 241#define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 242#define CONFIG_SYS_I2C_SLAVE            0x7F
 243#endif
 244
 245#define CONFIG_RTC_PCF8563      1               /* enable I2C support for */
 246                                                                        /* Philips PCF8563 RTC */
 247#define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* Philips PCF8563 RTC address */
 248
 249/*--------------------------------------------------------------------
 250 *      Memory Control Configuration Register values
 251 *      - see sec. 4.12 of MPC8245 UM
 252 *------------------------------------------------------------------*/
 253
 254/**** MCCR1 ****/
 255#define CONFIG_SYS_ROMNAL           0
 256#define CONFIG_SYS_ROMFAL           10          /* (tacc=70ns)*mem_freq - 2,
 257                                                                        mem_freq = 100MHz */
 258
 259#define CONFIG_SYS_BANK7_ROW    0               /* SDRAM bank 7-0 row address */
 260#define CONFIG_SYS_BANK6_ROW    0               /*      bit count */
 261#define CONFIG_SYS_BANK5_ROW    0
 262#define CONFIG_SYS_BANK4_ROW    0
 263#define CONFIG_SYS_BANK3_ROW    0
 264#define CONFIG_SYS_BANK2_ROW    0
 265#define CONFIG_SYS_BANK1_ROW    2
 266#define CONFIG_SYS_BANK0_ROW    2
 267
 268/**** MCCR2, refresh interval clock cycles ****/
 269#define CONFIG_SYS_REFINT           480     /* 33 MHz SDRAM clock was 480 */
 270
 271/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
 272#define CONFIG_SYS_BSTOPRE          1023        /* burst to precharge[0..9], */
 273                                                                /* sets open page interval */
 274
 275/**** MCCR3 ****/
 276#define CONFIG_SYS_REFREC           7       /* Refresh to activate interval, trc */
 277
 278/**** MCCR4 ****/
 279#define CONFIG_SYS_PRETOACT         2       /* trp */
 280#define CONFIG_SYS_ACTTOPRE         7       /* trcd + (burst length - 1) + trdl */
 281#define CONFIG_SYS_SDMODE_CAS_LAT  3        /* SDMODE CAS latancy */
 282#define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type, sequential */
 283#define CONFIG_SYS_ACTORW               2               /* trcd min */
 284#define CONFIG_SYS_DBUS_SIZE2           1               /* set for 8-bit RCS1, clear for 32,64 */
 285#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 286#define CONFIG_SYS_EXTROM           0                   /* we don't need extended ROM space */
 287#define CONFIG_SYS_REGDIMM          0
 288
 289/* calculate according to formula in sec. 6-22 of 8245 UM */
 290#define CONFIG_SYS_PGMAX           50           /* how long the 8245 retains the */
 291                                                                        /* currently accessed page in memory */
 292                                                                        /* was 45 */
 293
 294#define CONFIG_SYS_SDRAM_DSCD   0x20    /* SDRAM data in sample clock delay - note */
 295                                                                /* bits 7,6, and 3-0 MUST be 0 */
 296
 297#if 0
 298#define CONFIG_SYS_DLL_MAX_DELAY        0x04
 299#else
 300#define CONFIG_SYS_DLL_MAX_DELAY        0
 301#endif
 302#if 0                                                   /* need for 33MHz SDRAM */
 303#define CONFIG_SYS_DLL_EXTEND   0x80
 304#else
 305#define CONFIG_SYS_DLL_EXTEND   0
 306#endif
 307#define CONFIG_SYS_PCI_HOLD_DEL 0x20
 308
 309
 310/* Memory bank settings.
 311 * Only bits 20-29 are actually used from these values to set the
 312 * start/end addresses. The upper two bits will always be 0, and the lower
 313 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 314 * address. Refer to the MPC8245 user manual.
 315 */
 316
 317#define CONFIG_SYS_BANK0_START      0x00000000
 318#define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
 319#define CONFIG_SYS_BANK0_ENABLE    1
 320#define CONFIG_SYS_BANK1_START      CONFIG_SYS_MAX_RAM_SIZE/2
 321#define CONFIG_SYS_BANK1_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 322#define CONFIG_SYS_BANK1_ENABLE    1
 323#define CONFIG_SYS_BANK2_START      0x3ff00000          /* not available in this design */
 324#define CONFIG_SYS_BANK2_END        0x3fffffff
 325#define CONFIG_SYS_BANK2_ENABLE    0
 326#define CONFIG_SYS_BANK3_START      0x3ff00000
 327#define CONFIG_SYS_BANK3_END        0x3fffffff
 328#define CONFIG_SYS_BANK3_ENABLE    0
 329#define CONFIG_SYS_BANK4_START      0x3ff00000
 330#define CONFIG_SYS_BANK4_END        0x3fffffff
 331#define CONFIG_SYS_BANK4_ENABLE    0
 332#define CONFIG_SYS_BANK5_START      0x3ff00000
 333#define CONFIG_SYS_BANK5_END        0x3fffffff
 334#define CONFIG_SYS_BANK5_ENABLE    0
 335#define CONFIG_SYS_BANK6_START      0x3ff00000
 336#define CONFIG_SYS_BANK6_END        0x3fffffff
 337#define CONFIG_SYS_BANK6_ENABLE    0
 338#define CONFIG_SYS_BANK7_START      0x3ff00000
 339#define CONFIG_SYS_BANK7_END        0x3fffffff
 340#define CONFIG_SYS_BANK7_ENABLE    0
 341
 342/*--------------------------------------------------------------------*/
 343/* 4.4 - Output Driver Control Register */
 344/*--------------------------------------------------------------------*/
 345#define CONFIG_SYS_ODCR     0xe5
 346
 347/*--------------------------------------------------------------------*/
 348/* 4.8 - Error Handling Registers */
 349/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
 350#define CONFIG_SYS_ERRENR1      0x11    /* enable SDRAM refresh overflow error */
 351
 352/* SDRAM 0-256 MB */
 353#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 354/*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
 355#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 356
 357/* stack in dcache */
 358#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 359#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 360
 361
 362#define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 363#define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
 364
 365/* PCI memory */
 366/*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
 367/*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
 368
 369/*Flash, config addrs, etc. */
 370#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 371#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 372
 373#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 374#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 375#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 376#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 377#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 378#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 379#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 380#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 381
 382/*
 383 * For booting Linux, the board info and command line data
 384 * have to be in the first 8 MB of memory, since this is
 385 * the maximum mapped by the Linux kernel during initialization.
 386 */
 387#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 388
 389/*-----------------------------------------------------------------------
 390 * FLASH organization
 391 *----------------------------------------------------------------------*/
 392#define CONFIG_SYS_FLASH_BASE       0xFF800000
 393#define CONFIG_SYS_MAX_FLASH_BANKS      1                       /* Max number of flash banks */
 394
 395/*      NOTE: environment is not EMBEDDED in the u-boot code.
 396        It's stored in flash in its own separate sector.  */
 397#define CONFIG_ENV_IS_IN_FLASH      1
 398
 399#if 1   /* AMD AM29LV033C */
 400#define CONFIG_SYS_MAX_FLASH_SECT       64              /* Max number of sectors in one bank */
 401#define CONFIG_ENV_ADDR         0xFFBF0000      /* flash sector SA63 */
 402#define CONFIG_ENV_SECT_SIZE    (64*1024)       /* Size of the Environment Sector */
 403#else   /* AMD AM29LV116D */
 404#define CONFIG_SYS_MAX_FLASH_SECT       35      /* Max number of sectors in one bank */
 405#define CONFIG_ENV_ADDR         0xFF9FA000      /* flash sector SA33 */
 406#define CONFIG_ENV_SECT_SIZE    (8*1024)        /* Size of the Environment Sector */
 407#endif /* #if */
 408
 409#define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE            /* Size of the Environment */
 410#define CONFIG_ENV_OFFSET               0                       /* starting right at the beginning */
 411
 412#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 413#define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout for Flash Write (in ms)      */
 414
 415#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 416#undef CONFIG_SYS_RAMBOOT
 417#else
 418#define CONFIG_SYS_RAMBOOT
 419#endif
 420
 421
 422/*-----------------------------------------------------------------------
 423 * Cache Configuration
 424 */
 425#define CONFIG_SYS_CACHELINE_SIZE       32
 426#if defined(CONFIG_CMD_KGDB)
 427#  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 428#endif
 429
 430#endif  /* __CONFIG_H */
 431