LXR uboot/arch/arm/cpu/pxa/cpu.c

   1/*
   2 * (C) Copyright 2002
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 *
   6 * (C) Copyright 2002
   7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8 * Alex Zuepke <azu@sysgo.de>
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29/*
  30 * CPU specific code
  31 */
  32
  33#include <asm/io.h>
  34#include <asm/system.h>
  35#include <command.h>
  36#include <common.h>
  37#include <asm/arch/pxa-regs.h>
  38
  39static void cache_flush(void);
  40
  41int cleanup_before_linux (void)
  42{
  43        /*
  44         * this function is called just before we call linux
  45         * it prepares the processor for linux
  46         *
  47         * just disable everything that can disturb booting linux
  48         */
  49
  50        disable_interrupts ();
  51
  52        /* turn off I-cache */
  53        icache_disable();
  54        dcache_disable();
  55
  56        /* flush I-cache */
  57        cache_flush();
  58
  59        return (0);
  60}
  61
  62/* flush I/D-cache */
  63static void cache_flush (void)
  64{
  65        unsigned long i = 0;
  66
  67        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  68}
  69
  70#ifndef CONFIG_CPU_MONAHANS
  71void set_GPIO_mode(int gpio_mode)
  72{
  73        int gpio = gpio_mode & GPIO_MD_MASK_NR;
  74        int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
  75        int val;
  76
  77        /* This below changes direction setting of GPIO "gpio" */
  78        val = readl(GPDR(gpio));
  79
  80        if (gpio_mode & GPIO_MD_MASK_DIR)
  81                val |= GPIO_bit(gpio);
  82        else
  83                val &= ~GPIO_bit(gpio);
  84
  85        writel(val, GPDR(gpio));
  86
  87        /* This below updates only AF of GPIO "gpio" */
  88        val = readl(GAFR(gpio));
  89        val &= ~(0x3 << (((gpio) & 0xf) * 2));
  90        val |= fn << (((gpio) & 0xf) * 2);
  91        writel(val, GAFR(gpio));
  92}
  93#endif /* CONFIG_CPU_MONAHANS */
  94
  95void pxa_wait_ticks(int ticks)
  96{
  97        writel(0, OSCR);
  98        while (readl(OSCR) < ticks)
  99                asm volatile("":::"memory");
 100}
 101
 102inline void writelrb(uint32_t val, uint32_t addr)
 103{
 104        writel(val, addr);
 105        asm volatile("":::"memory");
 106        readl(addr);
 107        asm volatile("":::"memory");
 108}
 109
 110void pxa_dram_init(void)
 111{
 112        uint32_t tmp;
 113        int i;
 114        /*
 115         * 1) Initialize Asynchronous static memory controller
 116         */
 117
 118        writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
 119        writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
 120        writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
 121        /*
 122         * 2) Initialize Card Interface
 123         */
 124
 125        /* MECR: Memory Expansion Card Register */
 126        writelrb(CONFIG_SYS_MECR_VAL, MECR);
 127        /* MCMEM0: Card Interface slot 0 timing */
 128        writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
 129        /* MCMEM1: Card Interface slot 1 timing */
 130        writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
 131        /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
 132        writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
 133        /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
 134        writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
 135        /* MCIO0: Card Interface I/O Space Timing, slot 0 */
 136        writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
 137        /* MCIO1: Card Interface I/O Space Timing, slot 1 */
 138        writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
 139
 140        /*
 141         * 3) Configure Fly-By DMA register
 142         */
 143
 144        writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
 145
 146        /*
 147         * 4) Initialize Timing for Sync Memory (SDCLK0)
 148         */
 149
 150        /*
 151         * Before accessing MDREFR we need a valid DRI field, so we set
 152         * this to power on defaults + DRI field.
 153         */
 154
 155        /* Read current MDREFR config and zero out DRI */
 156        tmp = readl(MDREFR) & ~0xfff;
 157        /* Add user-specified DRI */
 158        tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
 159        /* Configure important bits */
 160        tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
 161        tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
 162
 163        /* Write MDREFR back */
 164        writelrb(tmp, MDREFR);
 165
 166        /*
 167         * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
 168         */
 169
 170        /* Initialize SXCNFG register. Assert the enable bits.
 171         *
 172         * Write SXMRS to cause an MRS command to all enabled banks of
 173         * synchronous static memory. Note that SXLCR need not be written
 174         * at this time.
 175         */
 176        writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
 177
 178        /*
 179         * 6) Initialize SDRAM
 180         */
 181
 182        writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
 183        writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
 184
 185        /*
 186         * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
 187         *    but not enable each SDRAM partition pair.
 188         */
 189
 190        writelrb(CONFIG_SYS_MDCNFG_VAL &
 191                ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
 192        /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
 193        pxa_wait_ticks(0x300);
 194
 195        /*
 196         * 8) Trigger a number (usually 8) refresh cycles by attempting
 197         *    non-burst read or write accesses to disabled SDRAM, as commonly
 198         *    specified in the power up sequence documented in SDRAM data
 199         *    sheets. The address(es) used for this purpose must not be
 200         *    cacheable.
 201         */
 202        for (i = 9; i >= 0; i--) {
 203                writel(i, 0xa0000000);
 204                asm volatile("":::"memory");
 205        }
 206        /*
 207         * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
 208         */
 209
 210        tmp = CONFIG_SYS_MDCNFG_VAL &
 211                (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
 212        tmp |= readl(MDCNFG);
 213        writelrb(tmp, MDCNFG);
 214
 215        /*
 216         * 10) Write MDMRS.
 217         */
 218
 219        writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
 220
 221        /*
 222         * 11) Enable APD
 223         */
 224
 225        if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
 226                tmp = readl(MDREFR);
 227                tmp |= MDREFR_APD;
 228                writelrb(tmp, MDREFR);
 229        }
 230}
 231
 232void pxa_gpio_setup(void)
 233{
 234        writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
 235        writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
 236        writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
 237#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 238        writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
 239#endif
 240
 241        writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
 242        writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
 243        writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
 244#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 245        writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
 246#endif
 247
 248        writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
 249        writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
 250        writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
 251#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 252        writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
 253#endif
 254
 255        writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
 256        writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
 257        writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
 258        writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
 259        writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
 260        writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
 261#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 262        writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
 263        writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
 264#endif
 265
 266        writel(CONFIG_SYS_PSSR_VAL, PSSR);
 267}
 268
 269void pxa_interrupt_setup(void)
 270{
 271        writel(0, ICLR);
 272        writel(0, ICMR);
 273#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 274        writel(0, ICLR2);
 275        writel(0, ICMR2);
 276#endif
 277}
 278
 279void pxa_clock_setup(void)
 280{
 281#ifndef CONFIG_CPU_MONAHANS
 282        writel(CONFIG_SYS_CKEN, CKEN);
 283        writel(CONFIG_SYS_CCCR, CCCR);
 284        asm volatile("mcr       p14, 0, %0, c6, c0, 0"::"r"(2));
 285#else
 286/* Set CKENA/CKENB/ACCR for MH */
 287#endif
 288
 289        /* enable the 32Khz oscillator for RTC and PowerManager */
 290        writel(OSCC_OON, OSCC);
 291        while(!(readl(OSCC) & OSCC_OOK))
 292                asm volatile("":::"memory");
 293}
 294
 295void pxa_wakeup(void)
 296{
 297        uint32_t rcsr;
 298
 299        rcsr = readl(RCSR);
 300        writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
 301
 302        /* Wakeup */
 303        if (rcsr & RCSR_SMR) {
 304                writel(PSSR_PH, PSSR);
 305                pxa_dram_init();
 306                icache_disable();
 307                dcache_disable();
 308                asm volatile("mov       pc, %0"::"r"(readl(PSSR)));
 309        }
 310}
 311
 312int arch_cpu_init(void)
 313{
 314        pxa_gpio_setup();
 315/*      pxa_wait_ticks(0x8000); */
 316        pxa_wakeup();
 317        pxa_interrupt_setup();
 318        pxa_clock_setup();
 319        return 0;
 320}
 321
 322void i2c_clk_enable(void)
 323{
 324        /* set the global I2C clock on */
 325#ifdef CONFIG_CPU_MONAHANS
 326        writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
 327#else
 328        writel(readl(CKEN) | CKEN14_I2C, CKEN);
 329#endif
 330}
 331