1/* 2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22#ifndef _EMIF_DEFS_H_ 23#define _EMIF_DEFS_H_ 24 25#include <asm/arch/hardware.h> 26 27struct davinci_emif_regs { 28 u_int32_t ercsr; 29 u_int32_t awccr; 30 u_int32_t sdbcr; 31 u_int32_t sdrcr; 32 u_int32_t ab1cr; 33 u_int32_t ab2cr; 34 u_int32_t ab3cr; 35 u_int32_t ab4cr; 36 u_int32_t sdtimr; 37 u_int32_t ddrsr; 38 u_int32_t ddrphycr; 39 u_int32_t ddrphysr; 40 u_int32_t totar; 41 u_int32_t totactr; 42 u_int32_t ddrphyid_rev; 43 u_int32_t sdsretr; 44 u_int32_t eirr; 45 u_int32_t eimr; 46 u_int32_t eimsr; 47 u_int32_t eimcr; 48 u_int32_t ioctrlr; 49 u_int32_t iostatr; 50 u_int8_t rsvd0[8]; 51 u_int32_t nandfcr; 52 u_int32_t nandfsr; 53 u_int8_t rsvd1[8]; 54 u_int32_t nandfecc[4]; 55 u_int8_t rsvd2[60]; 56 u_int32_t nand4biteccload; 57 u_int32_t nand4bitecc[4]; 58 u_int32_t nanderradd1; 59 u_int32_t nanderradd2; 60 u_int32_t nanderrval1; 61 u_int32_t nanderrval2; 62}; 63 64#define davinci_emif_regs \ 65 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) 66 67#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) 68#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) 69#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) 70#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) 71#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) 72#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) 73 74/* Chip Select setup */ 75#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) 76#define DAVINCI_ABCR_EXT_WAIT (1 << 30) 77#define DAVINCI_ABCR_WSETUP(n) (n << 26) 78#define DAVINCI_ABCR_WSTROBE(n) (n << 20) 79#define DAVINCI_ABCR_WHOLD(n) (n << 17) 80#define DAVINCI_ABCR_RSETUP(n) (n << 13) 81#define DAVINCI_ABCR_RSTROBE(n) (n << 7) 82#define DAVINCI_ABCR_RHOLD(n) (n << 4) 83#define DAVINCI_ABCR_TA(n) (n << 2) 84#define DAVINCI_ABCR_ASIZE_16BIT 1 85#define DAVINCI_ABCR_ASIZE_8BIT 0 86 87#endif 88