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33#ifndef __ASM_ARCH_HARDWARE_H
34#define __ASM_ARCH_HARDWARE_H
35
36#include <config.h>
37#include <asm/sizes.h>
38
39#define REG(addr) (*(volatile unsigned int *)(addr))
40#define REG_P(addr) ((volatile unsigned int *)(addr))
41
42typedef volatile unsigned int dv_reg;
43typedef volatile unsigned int * dv_reg_p;
44
45
46
47
48
49
50
51
52#ifndef CONFIG_SOC_DA8XX
53
54#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
55#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
56#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
57#define DAVINCI_UART0_BASE (0x01c20000)
58#define DAVINCI_UART1_BASE (0x01c20400)
59#define DAVINCI_I2C_BASE (0x01c21000)
60#define DAVINCI_TIMER0_BASE (0x01c21400)
61#define DAVINCI_TIMER1_BASE (0x01c21800)
62#define DAVINCI_WDOG_BASE (0x01c21c00)
63#define DAVINCI_PWM0_BASE (0x01c22000)
64#define DAVINCI_PWM1_BASE (0x01c22400)
65#define DAVINCI_PWM2_BASE (0x01c22800)
66#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
67#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
68#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
69#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
70#define DAVINCI_ARM_INTC_BASE (0x01c48000)
71#define DAVINCI_USB_OTG_BASE (0x01c64000)
72#define DAVINCI_CFC_ATA_BASE (0x01c66000)
73#define DAVINCI_SPI_BASE (0x01c66800)
74#define DAVINCI_GPIO_BASE (0x01c67000)
75#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
76#if !defined(CONFIG_SOC_DM646X)
77#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
78#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
79#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
80#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
81#endif
82#define DAVINCI_DDR_BASE (0x80000000)
83
84#ifdef CONFIG_SOC_DM644X
85#define DAVINCI_UART2_BASE 0x01c20800
86#define DAVINCI_UHPI_BASE 0x01c67800
87#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
88#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
89#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
90#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
91#define DAVINCI_IMCOP_BASE 0x01cc0000
92#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
93#define DAVINCI_VLYNQ_BASE 0x01e01000
94#define DAVINCI_ASP_BASE 0x01e02000
95#define DAVINCI_MMC_SD_BASE 0x01e10000
96#define DAVINCI_MS_BASE 0x01e20000
97#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
98
99#elif defined(CONFIG_SOC_DM355)
100#define DAVINCI_MMC_SD1_BASE 0x01e00000
101#define DAVINCI_ASP0_BASE 0x01e02000
102#define DAVINCI_ASP1_BASE 0x01e04000
103#define DAVINCI_UART2_BASE 0x01e06000
104#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
105#define DAVINCI_MMC_SD0_BASE 0x01e11000
106
107#elif defined(CONFIG_SOC_DM365)
108#define DAVINCI_MMC_SD1_BASE 0x01d00000
109#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
110#define DAVINCI_MMC_SD0_BASE 0x01d11000
111
112#elif defined(CONFIG_SOC_DM646X)
113#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
114#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
115#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
116#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
117#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
118
119#endif
120
121#else
122
123#define DAVINCI_UART0_BASE 0x01c42000
124#define DAVINCI_UART1_BASE 0x01d0c000
125#define DAVINCI_UART2_BASE 0x01d0d000
126#define DAVINCI_I2C0_BASE 0x01c22000
127#define DAVINCI_I2C1_BASE 0x01e28000
128#define DAVINCI_TIMER0_BASE 0x01c20000
129#define DAVINCI_TIMER1_BASE 0x01c21000
130#define DAVINCI_WDOG_BASE 0x01c21000
131#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
132#define DAVINCI_PSC0_BASE 0x01c10000
133#define DAVINCI_PSC1_BASE 0x01e27000
134#define DAVINCI_SPI0_BASE 0x01c41000
135#define DAVINCI_USB_OTG_BASE 0x01e00000
136#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
137 0x01e12000 : 0x01f0e000)
138#define DAVINCI_GPIO_BASE 0x01e26000
139#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
140#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
141#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
142#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
143#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
144#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
145#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
146#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
147#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
148#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
149#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
150#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
151#define DAVINCI_INTC_BASE 0xfffee000
152#define DAVINCI_BOOTCFG_BASE 0x01c14000
153#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
154
155#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
156#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
157#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
158#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
159#endif
160
161
162#define DAVINCI_GPSC_ARMDOMAIN 0
163#define DAVINCI_GPSC_DSPDOMAIN 1
164
165#ifndef CONFIG_SOC_DA8XX
166
167#define DAVINCI_LPSC_VPSSMSTR 0
168#define DAVINCI_LPSC_VPSSSLV 1
169#define DAVINCI_LPSC_TPCC 2
170#define DAVINCI_LPSC_TPTC0 3
171#define DAVINCI_LPSC_TPTC1 4
172#define DAVINCI_LPSC_EMAC 5
173#define DAVINCI_LPSC_EMAC_WRAPPER 6
174#define DAVINCI_LPSC_MDIO 7
175#define DAVINCI_LPSC_IEEE1394 8
176#define DAVINCI_LPSC_USB 9
177#define DAVINCI_LPSC_ATA 10
178#define DAVINCI_LPSC_VLYNQ 11
179#define DAVINCI_LPSC_UHPI 12
180#define DAVINCI_LPSC_DDR_EMIF 13
181#define DAVINCI_LPSC_AEMIF 14
182#define DAVINCI_LPSC_MMC_SD 15
183#define DAVINCI_LPSC_MEMSTICK 16
184#define DAVINCI_LPSC_McBSP 17
185#define DAVINCI_LPSC_I2C 18
186#define DAVINCI_LPSC_UART0 19
187#define DAVINCI_LPSC_UART1 20
188#define DAVINCI_LPSC_UART2 21
189#define DAVINCI_LPSC_SPI 22
190#define DAVINCI_LPSC_PWM0 23
191#define DAVINCI_LPSC_PWM1 24
192#define DAVINCI_LPSC_PWM2 25
193#define DAVINCI_LPSC_GPIO 26
194#define DAVINCI_LPSC_TIMER0 27
195#define DAVINCI_LPSC_TIMER1 28
196#define DAVINCI_LPSC_TIMER2 29
197#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
198#define DAVINCI_LPSC_ARM 31
199#define DAVINCI_LPSC_SCR2 32
200#define DAVINCI_LPSC_SCR3 33
201#define DAVINCI_LPSC_SCR4 34
202#define DAVINCI_LPSC_CROSSBAR 35
203#define DAVINCI_LPSC_CFG27 36
204#define DAVINCI_LPSC_CFG3 37
205#define DAVINCI_LPSC_CFG5 38
206#define DAVINCI_LPSC_GEM 39
207#define DAVINCI_LPSC_IMCOP 40
208
209#define DAVINCI_DM646X_LPSC_EMAC 14
210#define DAVINCI_DM646X_LPSC_UART0 26
211#define DAVINCI_DM646X_LPSC_I2C 31
212#define DAVINCI_DM646X_LPSC_TIMER0 34
213
214#else
215
216enum davinci_lpsc_ids {
217 DAVINCI_LPSC_TPCC = 0,
218 DAVINCI_LPSC_TPTC0,
219 DAVINCI_LPSC_TPTC1,
220 DAVINCI_LPSC_AEMIF,
221 DAVINCI_LPSC_SPI0,
222 DAVINCI_LPSC_MMC_SD,
223 DAVINCI_LPSC_AINTC,
224 DAVINCI_LPSC_ARM_RAM_ROM,
225 DAVINCI_LPSC_SECCTL_KEYMGR,
226 DAVINCI_LPSC_UART0,
227 DAVINCI_LPSC_SCR0,
228 DAVINCI_LPSC_SCR1,
229 DAVINCI_LPSC_SCR2,
230 DAVINCI_LPSC_DMAX,
231 DAVINCI_LPSC_ARM,
232 DAVINCI_LPSC_GEM,
233
234 DAVINCI_LPSC_PSC1_BASE = 32,
235 DAVINCI_LPSC_USB11,
236 DAVINCI_LPSC_USB20,
237 DAVINCI_LPSC_GPIO,
238 DAVINCI_LPSC_UHPI,
239 DAVINCI_LPSC_EMAC,
240 DAVINCI_LPSC_DDR_EMIF,
241 DAVINCI_LPSC_McASP0,
242 DAVINCI_LPSC_McASP1,
243 DAVINCI_LPSC_McASP2,
244 DAVINCI_LPSC_SPI1,
245 DAVINCI_LPSC_I2C1,
246 DAVINCI_LPSC_UART1,
247 DAVINCI_LPSC_UART2,
248 DAVINCI_LPSC_LCDC,
249 DAVINCI_LPSC_ePWM,
250 DAVINCI_LPSC_eCAP,
251 DAVINCI_LPSC_eQEP,
252 DAVINCI_LPSC_SCR_P0,
253 DAVINCI_LPSC_SCR_P1,
254 DAVINCI_LPSC_CR_P3,
255 DAVINCI_LPSC_L3_CBA_RAM
256};
257
258#endif
259
260void lpsc_on(unsigned int id);
261void dsp_on(void);
262
263void davinci_enable_uart0(void);
264void davinci_enable_emac(void);
265void davinci_enable_i2c(void);
266void davinci_errata_workarounds(void);
267
268#ifndef CONFIG_SOC_DA8XX
269
270
271#define PSC_CHP_SHRTSW (0x01c40038)
272#define PSC_GBLCTL (0x01c41010)
273#define PSC_EPCPR (0x01c41070)
274#define PSC_EPCCR (0x01c41078)
275#define PSC_PTCMD (0x01c41120)
276#define PSC_PTSTAT (0x01c41128)
277#define PSC_PDSTAT (0x01c41200)
278#define PSC_PDSTAT1 (0x01c41204)
279#define PSC_PDCTL (0x01c41300)
280#define PSC_PDCTL1 (0x01c41304)
281
282#define PSC_MDCTL_BASE (0x01c41a00)
283#define PSC_MDSTAT_BASE (0x01c41800)
284
285#define VDD3P3V_PWDN (0x01c40048)
286#define UART0_PWREMU_MGMT (0x01c20030)
287
288#define PSC_SILVER_BULLET (0x01c41a20)
289
290#else
291
292#define PSC_PSC0_MODULE_ID_CNT 16
293#define PSC_PSC1_MODULE_ID_CNT 32
294
295struct davinci_psc_regs {
296 dv_reg revid;
297 dv_reg rsvd0[71];
298 dv_reg ptcmd;
299 dv_reg rsvd1;
300 dv_reg ptstat;
301 dv_reg rsvd2[437];
302 union {
303 struct {
304 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
305 dv_reg rsvd3[112];
306 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
307 } psc0;
308 struct {
309 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
310 dv_reg rsvd3[96];
311 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
312 } psc1;
313 };
314};
315
316#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
317#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
318
319#endif
320
321#ifndef CONFIG_SOC_DA8XX
322
323
324#define VBPR (0x20000020)
325
326
327
328
329#define PINMUX0 0x01c40000
330#define PINMUX1 0x01c40004
331#define PINMUX2 0x01c40008
332#define PINMUX3 0x01c4000c
333#define PINMUX4 0x01c40010
334
335#else
336
337struct davinci_pllc_regs {
338 dv_reg revid;
339 dv_reg rsvd1[56];
340 dv_reg rstype;
341 dv_reg rsvd2[6];
342 dv_reg pllctl;
343 dv_reg ocsel;
344 dv_reg rsvd3[2];
345 dv_reg pllm;
346 dv_reg prediv;
347 dv_reg plldiv1;
348 dv_reg plldiv2;
349 dv_reg plldiv3;
350 dv_reg oscdiv;
351 dv_reg postdiv;
352 dv_reg rsvd4[3];
353 dv_reg pllcmd;
354 dv_reg pllstat;
355 dv_reg alnctl;
356 dv_reg dchange;
357 dv_reg cken;
358 dv_reg ckstat;
359 dv_reg systat;
360 dv_reg rsvd5[3];
361 dv_reg plldiv4;
362 dv_reg plldiv5;
363 dv_reg plldiv6;
364 dv_reg plldiv7;
365 dv_reg rsvd6[32];
366 dv_reg emucnt0;
367 dv_reg emucnt1;
368};
369
370#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
371#define DAVINCI_PLLC_DIV_MASK 0x1f
372
373#define ASYNC3 get_async3_src()
374#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
375#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
376
377enum davinci_clk_ids {
378 DAVINCI_SPI0_CLKID = 2,
379 DAVINCI_UART2_CLKID = 2,
380 DAVINCI_MDIO_CLKID = 4,
381 DAVINCI_ARM_CLKID = 6,
382 DAVINCI_PLLM_CLKID = 0xff,
383 DAVINCI_PLLC_CLKID = 0x100,
384 DAVINCI_AUXCLK_CLKID = 0x101
385};
386
387int clk_get(enum davinci_clk_ids id);
388
389
390struct davinci_syscfg_regs {
391 dv_reg revid;
392 dv_reg rsvd[13];
393 dv_reg kick0;
394 dv_reg kick1;
395 dv_reg rsvd1[56];
396 dv_reg pinmux[20];
397 dv_reg suspsrc;
398 dv_reg chipsig;
399 dv_reg chipsig_clr;
400 dv_reg cfgchip0;
401 dv_reg cfgchip1;
402 dv_reg cfgchip2;
403 dv_reg cfgchip3;
404 dv_reg cfgchip4;
405};
406
407#define davinci_syscfg_regs \
408 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
409
410
411#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
412#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
413#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
414#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
415#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
416#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
417
418
419struct davinci_aintc_regs {
420 dv_reg revid;
421 dv_reg cr;
422 dv_reg dummy0[2];
423 dv_reg ger;
424 dv_reg dummy1[219];
425 dv_reg ecr1;
426 dv_reg ecr2;
427 dv_reg ecr3;
428 dv_reg dummy2[1117];
429 dv_reg hier;
430};
431
432#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
433
434struct davinci_uart_ctrl_regs {
435 dv_reg revid1;
436 dv_reg revid2;
437 dv_reg pwremu_mgmt;
438 dv_reg mdr;
439};
440
441#define DAVINCI_UART_CTRL_BASE 0x28
442#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
443#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
444#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
445
446#define davinci_uart0_ctrl_regs \
447 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
448#define davinci_uart1_ctrl_regs \
449 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
450#define davinci_uart2_ctrl_regs \
451 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
452
453
454#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
455#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
456#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
457
458static inline int cpu_is_da830(void)
459{
460 unsigned int jtag_id = REG(JTAG_ID_REG);
461 unsigned short part_no = (jtag_id >> 12) & 0xffff;
462
463 return ((part_no == 0xb7df) ? 1 : 0);
464}
465static inline int cpu_is_da850(void)
466{
467 unsigned int jtag_id = REG(JTAG_ID_REG);
468 unsigned short part_no = (jtag_id >> 12) & 0xffff;
469
470 return ((part_no == 0xb7d1) ? 1 : 0);
471}
472
473static inline int get_async3_src(void)
474{
475 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
476 PLL1_SYSCLK2 : 2;
477}
478
479#endif
480
481#endif
482
