LXR uboot/arch/m68k/include/asm/coldfire/dspi.h

   1/*
   2 * MCF5227x Internal Memory Map
   3 *
   4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#ifndef __DSPI_H__
  27#define __DSPI_H__
  28
  29/* DMA Serial Peripheral Interface (DSPI) */
  30typedef struct dspi {
  31        u32 mcr;        /* 0x00 */
  32        u32 resv0;      /* 0x04 */
  33        u32 tcr;        /* 0x08 */
  34        u32 ctar[8];    /* 0x0C - 0x28 */
  35        u32 sr;         /* 0x2C */
  36        u32 irsr;       /* 0x30 */
  37        u32 tfr;        /* 0x34 - PUSHR */
  38        u16 resv1;      /* 0x38 */
  39        u16 rfr;        /* 0x3A - POPR */
  40#ifdef CONFIG_MCF547x_8x
  41        u32 tfdr[4];    /* 0x3C */
  42        u8 resv2[0x30]; /* 0x40 */
  43        u32 rfdr[4];    /* 0x7C */
  44#else
  45        u32 tfdr[16];   /* 0x3C */
  46        u32 rfdr[16];   /* 0x7C */
  47#endif
  48} dspi_t;
  49
  50/* Module configuration */
  51#define DSPI_MCR_MSTR                   (0x80000000)
  52#define DSPI_MCR_CSCK                   (0x40000000)
  53#define DSPI_MCR_DCONF(x)               (((x)&0x03)<<28)
  54#define DSPI_MCR_FRZ                    (0x08000000)
  55#define DSPI_MCR_MTFE                   (0x04000000)
  56#define DSPI_MCR_PCSSE                  (0x02000000)
  57#define DSPI_MCR_ROOE                   (0x01000000)
  58#define DSPI_MCR_CSIS7                  (0x00800000)
  59#define DSPI_MCR_CSIS6                  (0x00400000)
  60#define DSPI_MCR_CSIS5                  (0x00200000)
  61#define DSPI_MCR_CSIS4                  (0x00100000)
  62#define DSPI_MCR_CSIS3                  (0x00080000)
  63#define DSPI_MCR_CSIS2                  (0x00040000)
  64#define DSPI_MCR_CSIS1                  (0x00020000)
  65#define DSPI_MCR_CSIS0                  (0x00010000)
  66#define DSPI_MCR_MDIS                   (0x00004000)
  67#define DSPI_MCR_DTXF                   (0x00002000)
  68#define DSPI_MCR_DRXF                   (0x00001000)
  69#define DSPI_MCR_CTXF                   (0x00000800)
  70#define DSPI_MCR_CRXF                   (0x00000400)
  71#define DSPI_MCR_SMPL_PT(x)             (((x)&0x03)<<8)
  72#define DSPI_MCR_HALT                   (0x00000001)
  73
  74/* Transfer count */
  75#define DSPI_TCR_SPI_TCNT(x)            (((x)&0x0000FFFF)<<16)
  76
  77/* Clock and transfer attributes */
  78#define DSPI_CTAR_DBR                   (0x80000000)
  79#define DSPI_CTAR_TRSZ(x)               (((x)&0x0F)<<27)
  80#define DSPI_CTAR_CPOL                  (0x04000000)
  81#define DSPI_CTAR_CPHA                  (0x02000000)
  82#define DSPI_CTAR_LSBFE                 (0x01000000)
  83#define DSPI_CTAR_PCSSCK(x)             (((x)&0x03)<<22)
  84#define DSPI_CTAR_PCSSCK_7CLK           (0x00A00000)
  85#define DSPI_CTAR_PCSSCK_5CLK           (0x00800000)
  86#define DSPI_CTAR_PCSSCK_3CLK           (0x00400000)
  87#define DSPI_CTAR_PCSSCK_1CLK           (0x00000000)
  88#define DSPI_CTAR_PASC(x)               (((x)&0x03)<<20)
  89#define DSPI_CTAR_PASC_7CLK             (0x00300000)
  90#define DSPI_CTAR_PASC_5CLK             (0x00200000)
  91#define DSPI_CTAR_PASC_3CLK             (0x00100000)
  92#define DSPI_CTAR_PASC_1CLK             (0x00000000)
  93#define DSPI_CTAR_PDT(x)                (((x)&0x03)<<18)
  94#define DSPI_CTAR_PDT_7CLK              (0x000A0000)
  95#define DSPI_CTAR_PDT_5CLK              (0x00080000)
  96#define DSPI_CTAR_PDT_3CLK              (0x00040000)
  97#define DSPI_CTAR_PDT_1CLK              (0x00000000)
  98#define DSPI_CTAR_PBR(x)                (((x)&0x03)<<16)
  99#define DSPI_CTAR_PBR_7CLK              (0x00030000)
 100#define DSPI_CTAR_PBR_5CLK              (0x00020000)
 101#define DSPI_CTAR_PBR_3CLK              (0x00010000)
 102#define DSPI_CTAR_PBR_1CLK              (0x00000000)
 103#define DSPI_CTAR_CSSCK(x)              (((x)&0x0F)<<12)
 104#define DSPI_CTAR_ASC(x)                (((x)&0x0F)<<8)
 105#define DSPI_CTAR_DT(x)                 (((x)&0x0F)<<4)
 106#define DSPI_CTAR_BR(x)                 (((x)&0x0F))
 107
 108/* Status */
 109#define DSPI_SR_TCF                     (0x80000000)
 110#define DSPI_SR_TXRXS                   (0x40000000)
 111#define DSPI_SR_EOQF                    (0x10000000)
 112#define DSPI_SR_TFUF                    (0x08000000)
 113#define DSPI_SR_TFFF                    (0x02000000)
 114#define DSPI_SR_RFOF                    (0x00080000)
 115#define DSPI_SR_RFDF                    (0x00020000)
 116#define DSPI_SR_TXCTR(x)                (((x)&0x0F)<<12)
 117#define DSPI_SR_TXPTR(x)                (((x)&0x0F)<<8)
 118#define DSPI_SR_RXCTR(x)                (((x)&0x0F)<<4)
 119#define DSPI_SR_RXPTR(x)                (((x)&0x0F))
 120
 121/* DMA/interrupt request selct and enable */
 122#define DSPI_IRSR_TCFE                  (0x80000000)
 123#define DSPI_IRSR_EOQFE                 (0x10000000)
 124#define DSPI_IRSR_TFUFE                 (0x08000000)
 125#define DSPI_IRSR_TFFFE                 (0x02000000)
 126#define DSPI_IRSR_TFFFS                 (0x01000000)
 127#define DSPI_IRSR_RFOFE                 (0x00080000)
 128#define DSPI_IRSR_RFDFE                 (0x00020000)
 129#define DSPI_IRSR_RFDFS                 (0x00010000)
 130
 131/* Transfer control - 32-bit access */
 132#define DSPI_TFR_CONT                   (0x80000000)
 133#define DSPI_TFR_CTAS(x)                (((x)&0x07)<<12)
 134#define DSPI_TFR_EOQ                    (0x08000000)
 135#define DSPI_TFR_CTCNT                  (0x04000000)
 136#define DSPI_TFR_CS7                    (0x00800000)
 137#define DSPI_TFR_CS6                    (0x00400000)
 138#define DSPI_TFR_CS5                    (0x00200000)
 139#define DSPI_TFR_CS4                    (0x00100000)
 140#define DSPI_TFR_CS3                    (0x00080000)
 141#define DSPI_TFR_CS2                    (0x00040000)
 142#define DSPI_TFR_CS1                    (0x00020000)
 143#define DSPI_TFR_CS0                    (0x00010000)
 144
 145/* Transfer Fifo */
 146#define DSPI_TFR_TXDATA(x)              (((x)&0xFFFF))
 147
 148/* Bit definitions and macros for DRFR */
 149#define DSPI_RFR_RXDATA(x)              (((x)&0xFFFF))
 150
 151/* Bit definitions and macros for DTFDR group */
 152#define DSPI_TFDR_TXDATA(x)             (((x)&0x0000FFFF))
 153#define DSPI_TFDR_TXCMD(x)              (((x)&0x0000FFFF)<<16)
 154
 155/* Bit definitions and macros for DRFDR group */
 156#define DSPI_RFDR_RXDATA(x)             (((x)&0x0000FFFF))
 157
 158#endif                          /* __DSPI_H__ */
 159