1/* 2 * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef fsl_mcdmafec_h 27#define fsl_mcdmafec_h 28 29/* Re-use of the definitions */ 30#include <asm/fec.h> 31 32typedef struct fecdma { 33 u32 rsvd0; /* 0x000 */ 34 u32 eir; /* 0x004 */ 35 u32 eimr; /* 0x008 */ 36 u32 rsvd1[6]; /* 0x00C - 0x023 */ 37 u32 ecr; /* 0x024 */ 38 u32 rsvd2[6]; /* 0x028 - 0x03F */ 39 u32 mmfr; /* 0x040 */ 40 u32 mscr; /* 0x044 */ 41 u32 rsvd3[7]; /* 0x048 - 0x063 */ 42 u32 mibc; /* 0x064 */ 43 u32 rsvd4[7]; /* 0x068 - 0x083 */ 44 u32 rcr; /* 0x084 */ 45 u32 rhr; /* 0x088 */ 46 u32 rsvd5[14]; /* 0x08C - 0x0C3 */ 47 u32 tcr; /* 0x0C4 */ 48 u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ 49 u32 palr; /* 0x0E4 */ 50 u32 paur; /* 0x0E8 */ 51 u32 opd; /* 0x0EC */ 52 u32 rsvd7[10]; /* 0x0F0 - 0x117 */ 53 u32 iaur; /* 0x118 */ 54 u32 ialr; /* 0x11C */ 55 u32 gaur; /* 0x120 */ 56 u32 galr; /* 0x124 */ 57 u32 rsvd8[7]; /* 0x128 - 0x143 */ 58 u32 tfwr; /* 0x144 */ 59 u32 rsvd9[14]; /* 0x148 - 0x17F */ 60 u32 fmc; /* 0x180 */ 61 u32 rfdr; /* 0x184 */ 62 u32 rfsr; /* 0x188 */ 63 u32 rfcr; /* 0x18C */ 64 u32 rlrfp; /* 0x190 */ 65 u32 rlwfp; /* 0x194 */ 66 u32 rfar; /* 0x198 */ 67 u32 rfrp; /* 0x19C */ 68 u32 rfwp; /* 0x1A0 */ 69 u32 tfdr; /* 0x1A4 */ 70 u32 tfsr; /* 0x1A8 */ 71 u32 tfcr; /* 0x1AC */ 72 u32 tlrfp; /* 0x1B0 */ 73 u32 tlwfp; /* 0x1B4 */ 74 u32 tfar; /* 0x1B8 */ 75 u32 tfrp; /* 0x1BC */ 76 u32 tfwp; /* 0x1C0 */ 77 u32 frst; /* 0x1C4 */ 78 u32 ctcwr; /* 0x1C8 */ 79} fecdma_t; 80 81struct fec_info_dma { 82 int index; 83 u32 iobase; 84 u32 pinmux; 85 u32 miibase; 86 int phy_addr; 87 int dup_spd; 88 char *phy_name; 89 int phyname_init; 90 cbd_t *rxbd; /* Rx BD */ 91 cbd_t *txbd; /* Tx BD */ 92 uint rxIdx; 93 uint txIdx; 94 char *txbuf; 95 int initialized; 96 struct fec_info_dma *next; 97 98 u16 rxTask; /* DMA receive Task Number */ 99 u16 txTask; /* DMA Transmit Task Number */ 100 u16 rxPri; /* DMA Receive Priority */ 101 u16 txPri; /* DMA Transmit Priority */ 102 u16 rxInit; /* DMA Receive Initiator */ 103 u16 txInit; /* DMA Transmit Initiator */ 104 u16 usedTbdIdx; /* next transmit BD to clean */ 105 u16 cleanTbdNum; /* the number of available transmit BDs */ 106}; 107 108/* Bit definitions and macros for IEVENT */ 109#define FEC_EIR_TXERR (0x00040000) 110#define FEC_EIR_RXERR (0x00020000) 111#undef FEC_EIR_CLEAR_ALL 112#define FEC_EIR_CLEAR_ALL (0xFFFE0000) 113 114/* Bit definitions and macros for R_HASH */ 115#define FEC_RHASH_FCE_DC (0x80000000) 116#define FEC_RHASH_MULTCAST (0x40000000) 117#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) 118 119/* Bit definitions and macros for FEC_TFWR */ 120#undef FEC_TFWR_X_WMRK 121#undef FEC_TFWR_X_WMRK_64 122#undef FEC_TFWR_X_WMRK_128 123#undef FEC_TFWR_X_WMRK_192 124 125#define FEC_TFWR_X_WMRK(x) ((x)&0x0F) 126#define FEC_TFWR_X_WMRK_64 (0x00) 127#define FEC_TFWR_X_WMRK_128 (0x01) 128#define FEC_TFWR_X_WMRK_192 (0x02) 129#define FEC_TFWR_X_WMRK_256 (0x03) 130#define FEC_TFWR_X_WMRK_320 (0x04) 131#define FEC_TFWR_X_WMRK_384 (0x05) 132#define FEC_TFWR_X_WMRK_448 (0x06) 133#define FEC_TFWR_X_WMRK_512 (0x07) 134#define FEC_TFWR_X_WMRK_576 (0x08) 135#define FEC_TFWR_X_WMRK_640 (0x09) 136#define FEC_TFWR_X_WMRK_704 (0x0A) 137#define FEC_TFWR_X_WMRK_768 (0x0B) 138#define FEC_TFWR_X_WMRK_832 (0x0C) 139#define FEC_TFWR_X_WMRK_896 (0x0D) 140#define FEC_TFWR_X_WMRK_960 (0x0E) 141#define FEC_TFWR_X_WMRK_1024 (0x0F) 142 143/* FIFO definitions */ 144/* Bit definitions and macros for FSTAT */ 145#define FIFO_STAT_IP (0x80000000) 146#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) 147#define FIFO_STAT_FAE (0x00800000) 148#define FIFO_STAT_RXW (0x00400000) 149#define FIFO_STAT_UF (0x00200000) 150#define FIFO_STAT_OF (0x00100000) 151#define FIFO_STAT_FR (0x00080000) 152#define FIFO_STAT_FULL (0x00040000) 153#define FIFO_STAT_ALARM (0x00020000) 154#define FIFO_STAT_EMPTY (0x00010000) 155 156/* Bit definitions and macros for FCTRL */ 157#define FIFO_CTRL_WCTL (0x40000000) 158#define FIFO_CTRL_WFR (0x20000000) 159#define FIFO_CTRL_FRAME (0x08000000) 160#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) 161#define FIFO_CTRL_IPMASK (0x00800000) 162#define FIFO_CTRL_FAEMASK (0x00400000) 163#define FIFO_CTRL_RXWMASK (0x00200000) 164#define FIFO_CTRL_UFMASK (0x00100000) 165#define FIFO_CTRL_OFMASK (0x00080000) 166 167#endif /* fsl_mcdmafec_h */ 168