1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC405EZ_H_ 22#define _PPC405EZ_H_ 23 24#define CONFIG_NAND_NDFC 25 26/* Memory mapped register */ 27#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ 28 29#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 30#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) 31 32#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) 33#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) 34 35/* DCR register */ 36#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */ 37#define OCM0_PLBCR2 0x0021 /* OCM PLB3 Bank 2 Config */ 38#define OCM0_PLBBEAR 0x0022 /* OCM PLB3 Bus Error Add */ 39#define OCM0_DSRC1 0x0028 /* OCM D-side Bank 1 Config */ 40#define OCM0_DSRC2 0x0029 /* OCM D-side Bank 2 Config */ 41#define OCM0_ISRC1 0x002A /* OCM I-side Bank 1Config */ 42#define OCM0_ISRC2 0x002B /* OCM I-side Bank 2 Config */ 43#define OCM0_DISDPC 0x002C /* OCM D-/I-side Data Par Chk */ 44 45/* SDR register */ 46#define SDR0_NAND0 0x4000 47#define SDR0_ULTRA0 0x4040 48#define SDR0_ULTRA1 0x4050 49#define SDR0_ICINTSTAT 0x4510 50 51/* CPR register */ 52#define CPR0_PRIMAD 0x0080 53#define CPR0_PERD0 0x00e0 54#define CPR0_PERD1 0x00e1 55#define CPR0_PERC0 0x0180 56 57#define MAL_DCR_BASE 0x380 58 59#define SDR_NAND0_NDEN 0x80000000 60#define SDR_NAND0_NDBTEN 0x40000000 61#define SDR_NAND0_NDBADR_MASK 0x30000000 62#define SDR_NAND0_NDBPG_MASK 0x0f000000 63#define SDR_NAND0_NDAREN 0x00800000 64#define SDR_NAND0_NDRBEN 0x00400000 65 66#define SDR_ULTRA0_NDGPIOBP 0x80000000 67#define SDR_ULTRA0_CSN_MASK 0x78000000 68#define SDR_ULTRA0_CSNSEL0 0x40000000 69#define SDR_ULTRA0_CSNSEL1 0x20000000 70#define SDR_ULTRA0_CSNSEL2 0x10000000 71#define SDR_ULTRA0_CSNSEL3 0x08000000 72#define SDR_ULTRA0_EBCRDYEN 0x04000000 73#define SDR_ULTRA0_SPISSINEN 0x02000000 74#define SDR_ULTRA0_NFSRSTEN 0x01000000 75 76#define SDR_ULTRA1_LEDNENABLE 0x40000000 77 78#define SDR_ICRX_STAT 0x80000000 79#define SDR_ICTX0_STAT 0x40000000 80#define SDR_ICTX1_STAT 0x20000000 81 82#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ 83#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ 84#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ 85 86#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ 87 88#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ 89#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ 90#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ 91 92#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ 93#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ 94#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ 95#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ 96 97#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ 98#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ 99#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ 100#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ 101 102#endif /* _PPC405EZ_H_ */ 103