1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC460EX_GT_H_ 22#define _PPC460EX_GT_H_ 23 24#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ 25 26#define CONFIG_NAND_NDFC 27 28/* 29 * Some SoC specific registers 30 */ 31 32/* Memory mapped registers */ 33#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ 34 35#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 36#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) 37#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) 38#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) 39 40#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) 41#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) 42 43/* DCR */ 44#define AHB_TOP 0x00a4 45#define AHB_BOT 0x00a5 46 47/* SDR */ 48#define SDR0_PCI0 0x01c0 49#define SDR0_AHB_CFG 0x0370 50#define SDR0_USB2HOST_CFG 0x0371 51#define SDR0_ETH_PLL 0x4102 52#define SDR0_ETH_CFG 0x4103 53#define SDR0_ETH_STS 0x4104 54 55/* 56 * Register bits and masks 57 */ 58#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) 59#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) 60 61/* CUST0 Customer Configuration Register0 */ 62#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ 63#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ 64#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ 65#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ 66 67#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ 68#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ 69#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ 70 71#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ 72#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ 73#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ 74 75#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ 76#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) 77#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) 78 79#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ 80#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) 81#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) 82 83#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ 84#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ 85#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ 86 87#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ 88#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ 89#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ 90 91#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ 92#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) 93#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) 94 95#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ 96#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ 97#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ 98#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ 99#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ 100#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ 101#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ 102 103/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ 104#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /* Ethernet PLL lock indication */ 105 106/* Ethernet Configuration Register (SDR0_ETH_CFG) */ 107#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback 108 enable */ 109#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback 110 enable */ 111#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback 112 enable */ 113#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback 114 enable */ 115#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ 116#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ 117#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ 118#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ 119#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ 120#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ 121#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ 122#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ 123#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ 124#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ 125#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ 126#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ 127#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ 128#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ 129#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ 130#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ 131#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ 132#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge 133 selector */ 134#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge 135 selector */ 136 137#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ 138#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ 139#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ 140#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ 141#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ 142 transmitter 0 */ 143#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ 144 transmitter 1 */ 145#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ 146#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ 147#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ 148#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ 149#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ 150#define SDR0_SRST0_PCI 0x00100000 /* PCI */ 151#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ 152#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ 153#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ 154#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ 155#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ 156#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ 157#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ 158#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ 159#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ 160 transmitter 2 */ 161#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ 162#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ 163#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ 164#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ 165 transmitter 3 */ 166#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ 167 168#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ 169#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ 170#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ 171#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ 172#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ 173#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access 174 controller 0 */ 175#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access 176 controller 1 */ 177#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access 178 controller 2 */ 179#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access 180 controller 3 */ 181#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ 182#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ 183#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ 184#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ 185#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ 186#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ 187#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and 188 serdes */ 189#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ 190#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ 191#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ 192#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ 193#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ 194#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ 195#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ 196#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ 197#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ 198#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ 199#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ 200#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ 201#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ 202#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ 203#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ 204#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ 205 206#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ 207#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ 208#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ 209#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ 210#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ 211#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ 212#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ 213 214#define CPR0_ICFG_RLI_MASK 0x80000000 215 216#define CPR0_PLLC_RST 0x80000000 217#define CPR0_PLLC_ENG 0x40000000 218 219#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) 220#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) 221 222#endif /* _PPC460EX_GT_H_ */ 223