1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC460SX_H_ 22#define _PPC460SX_H_ 23 24#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ 25 26/* Memory mapped registers */ 27#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */ 28 29#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) 30#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 31 32#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) 33 34#define SDR0_SRST0_DMC 0x00200000 35 36#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ 37#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ 38#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ 39#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ 40#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ 41#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ 42#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ 43 44#endif /* _PPC460SX_H_ */ 45