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34#include <common.h>
35#include <command.h>
36#include <malloc.h>
37#include <asm/arch/ixp425.h>
38#include <asm/io.h>
39#include <miiphy.h>
40#ifdef CONFIG_PCI
41#include <pci.h>
42#include <asm/arch/ixp425pci.h>
43#endif
44
45#include "actux1_hw.h"
46
47DECLARE_GLOBAL_DATA_PTR;
48
49int board_early_init_f(void)
50{
51
52 writel(0x9d520003, IXP425_EXP_CS5);
53
54 writel(0x81860001, IXP425_EXP_CS6);
55
56 writel(0x80900003, IXP425_EXP_CS7);
57 return 0;
58}
59
60int board_init(void)
61{
62 gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
63
64
65 gd->bd->bi_boot_params = 0x00000100;
66
67 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
68 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
69
70
71 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
72 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
73
74
75 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
76 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
77 writel(0x011001FF, IXP425_GPIO_GPCLKR);
78
79 udelay(533);
80 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
81
82 ACTUX1_LED1(2);
83 ACTUX1_LED2(2);
84 ACTUX1_LED3(0);
85 ACTUX1_LED4(0);
86 ACTUX1_LED5(0);
87 ACTUX1_LED6(0);
88 ACTUX1_LED7(0);
89
90 ACTUX1_HS(ACTUX1_HS_DCD);
91
92 return 0;
93}
94
95
96
97
98int checkboard(void)
99{
100 char buf[64];
101 int i = getenv_f("serial#", buf, sizeof(buf));
102
103 puts("Board: AcTux-1 rev.");
104 putc(ACTUX1_BOARDREL + 'A' - 1);
105
106 if (i > 0) {
107 puts(", serial# ");
108 puts(buf);
109 }
110 putc('\n');
111
112 return 0;
113}
114
115
116
117
118
119
120
121u32 get_board_rev(void)
122{
123 return ACTUX1_BOARDREL;
124}
125
126int dram_init(void)
127{
128 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
129 return 0;
130}
131
132
133#ifdef CONFIG_PCI
134struct pci_controller hose;
135
136void pci_init_board(void)
137{
138 pci_ixp_init(&hose);
139}
140#endif
141
142void reset_phy(void)
143{
144 u16 id1, id2;
145
146
147 miiphy_reset("NPE0", CONFIG_PHY_ADDR);
148
149 miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
150 miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
151
152 id2 &= 0xFFF0;
153
154 if (id1 == 0x13 && id2 == 0x78e0) {
155
156
157
158
159
160
161 miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
162 } else if (id1 == 0x143 && id2 == 0xbc30) {
163
164 } else
165 printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
166}
167