LXR uboot/board/jornada/setup.S

   1/*
   2 * Memory Setup stuff - taken from blob memsetup.S
   3 *
   4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6 * 2004 (c) MontaVista Software, Inc.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27
  28#include "config.h"
  29#include "version.h"
  30
  31
  32/*-----------------------------------------------------------------------
  33 * Board defines:
  34 */
  35
  36#define MDCNFG          0x00
  37#define MDCAS00         0x04
  38#define MDCAS01         0x08
  39#define MDCAS02         0x0C
  40#define MSC0            0x10
  41#define MSC1            0x14
  42#define MECR            0x18
  43#define MDREFR          0x1C
  44#define MDCAS20         0x20
  45#define MDCAS21         0x24
  46#define MDCAS22         0x28
  47#define MSC2            0x2C
  48#define SMCNFG          0x30
  49
  50#define GPDR    0x04
  51#define GPSR    0x08
  52#define GPCR    0x0C
  53#define GAFR    0x1C
  54
  55#define PPDR    0x00
  56#define PPSR    0x04
  57#define PPAR    0x08
  58
  59#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
  60#define MDREFR_DRI(n_)   ((n_ & (0x00000fff)) << 4)
  61#define MDREFR_K0DB2 (1 << 18)
  62#define MDREFR_K1DB2 (1 << 22)
  63#define MDREFR_K2DB2 (1 << 26)
  64
  65#define MDREFR_K0RUN (1 << 17)
  66#define MDREFR_K1RUN (1 << 21)
  67#define MDREFR_K2RUN (1 << 25)
  68
  69#define MDREFR_SLFRSH (1 << 31)
  70#define MDREFR_E1PIN  (1 << 20)
  71
  72#define PSSR    0x04
  73#define PSSR_DH 0x00000008
  74#define POSR    0x08
  75#define RCSR    0x04
  76
  77/*-----------------------------------------------------------------------
  78 * Setup parameters for the board:
  79 */
  80MEM_BASE:       .long   0xa0000000
  81MEM_START:      .long   0xc0000000
  82PWR_BASE:       .word   0x90020000
  83RST_BASE:       .long   0x90030000
  84PPC_BASE:       .long   0x90060000
  85GPIO_BASE:      .long   0x90040000
  86IC_BASE:        .word   0x90050000
  87
  88cpuspeed:       .word   0xa0
  89/* calculated from old blob bootloader */
  90mdcnfg: .long   0x00037267      /* mdcnfg  0x00037267 */
  91mdcas00:        .long   0x5555557f      /* mdcas00 0x5555557f */
  92mdcas01:        .long   0x55555555      /* mdcas01 0x55555555 */
  93mdcas02:        .long   0x55555555      /* mdcas02 0x55555555 */
  94msc0:   .long   0xfff04f78              /* msc0    0xfff04f78 */
  95msc1:   .long   0xfff8fff0              /* msc1    0xfff8fff0 */
  96mecr:   .long   0x98c698c6      /* mecr    0x98c698c6 */
  97mdrefr: .long   0x067600c7      /* mdrefr  0x04340327 */
  98mdcas20:        .long   0xd1284142      /* mdcas20 0xd1284142 */
  99mdcas21:        .long   0x72249529      /* mdcas21 0x72249529 */
 100mdcas22:        .long   0x78414351      /* mdcas22 0x78414351 */
 101msc2:   .long   0x201d2959              /* msc2    0x201d2959 */
 102smcnfg: .long   0x00000000      /* smcnfg  0x00000000 */
 103
 104pin_set_out:    .long   0x37ff70
 105pin_set_dir:    .long   0x11480
 106
 107gpdr_set:       .long   0x0B3A0900
 108gpsr_set:       .long   0x02100800
 109gpcr_set:       .long   0x092A0100
 110gafr_set:       .long   0x08600000
 111
 112.globl lowlevel_init
 113lowlevel_init:
 114
 115
 116        /* this is required for flashing */
 117        ldr     r0, PPC_BASE
 118        ldr     r1, pin_set_out
 119        str     r1, [r0, #PPSR]
 120        ldr     r1, pin_set_dir
 121        str     r1, [r0, #PPDR]
 122
 123        /* Setting up the memory and stuff */
 124        /***********************************/
 125
 126        ldr     r0, MEM_BASE
 127
 128        ldr     r1, mdcnfg
 129        str     r1, [r0, #MDCNFG]
 130        ldr     r1, mdcas00
 131        str     r1, [r0, #MDCAS00]
 132        ldr     r1, mdcas01
 133        str     r1, [r0, #MDCAS01]
 134        ldr     r1, mdcas02
 135        str     r1, [r0, #MDCAS02]
 136        ldr     r1, mdcas20
 137        str     r1, [r0, #MDCAS20]
 138        ldr     r1, mdcas21
 139        str     r1, [r0, #MDCAS21]
 140        ldr     r1, mdcas22
 141        str     r1, [r0, #MDCAS22]
 142
 143        /* clear kxDB2 */
 144        ldr     r2, [r0, #MDREFR]
 145        bic     r2, r2, #MDREFR_K0DB2
 146        bic     r2, r2, #MDREFR_K1DB2
 147        bic     r2, r2, #MDREFR_K2DB2
 148        str     r2, [r0, #MDREFR]
 149
 150        ldr     r2, [r0, #MDREFR]
 151        orr r2, r2, #MDREFR_TRASR(7)
 152
 153        mov r4, #0x2000
 154        spin:   subs    r4, r4, #1
 155        bne     spin
 156
 157        ldr     r1, PWR_BASE
 158        mov     r2, #PSSR_DH
 159        str     r2, [r1, #PSSR]
 160
 161        ldr     r2, [r0, #MDREFR]
 162        bic     r2, r2, #MDREFR_K0DB2
 163        bic     r2, r2, #MDREFR_K1DB2
 164        bic     r2, r2, #MDREFR_K2DB2
 165        str     r2, [r0, #MDREFR]
 166
 167        ldr     r2, [r0, #MDREFR]
 168        orr     r2, r2, #MDREFR_TRASR(7)
 169        orr     r2, r2, #MDREFR_DRI(12)
 170        orr     r2, r2, #MDREFR_K0DB2
 171        orr     r2, r2, #MDREFR_K1DB2
 172        orr     r2, r2, #MDREFR_K2DB2
 173        str     r2, [r0, #MDREFR]
 174
 175        ldr     r2, [r0, #MDREFR]
 176        orr     r2, r2, #MDREFR_K0RUN
 177        orr     r2, r2, #MDREFR_K1RUN
 178        orr     r2, r2, #MDREFR_K2RUN
 179        str     r2, [r0, #MDREFR]
 180
 181        ldr     r2, [r0, #MDREFR]
 182        bic     r2, r2, #MDREFR_SLFRSH
 183        str     r2, [r0, #MDREFR]
 184
 185        ldr     r2, [r0, #MDREFR]
 186        orr     r2, r2, #MDREFR_E1PIN
 187        str     r2, [r0, #MDREFR]
 188
 189        ldr     r2, MEM_START
 190.rept   8
 191        ldr     r3, [r2]
 192.endr
 193
 194        ldr     r2, [r0, #MDCNFG]
 195        orr     r2, r2, #0x00000003
 196        orr     r2, r2, #0x00030000
 197        str     r2, [r0, #MDCNFG]
 198
 199        ldr     r1, msc0
 200        str     r1, [r0, #MSC0]
 201        ldr     r1, msc1
 202        str     r1, [r0, #MSC1]
 203        ldr     r1, msc2
 204        str     r1, [r0, #MSC2]
 205        ldr     r1, smcnfg
 206        str     r1, [r0, #SMCNFG]
 207        ldr     r1, mecr
 208        str     r1, [r0, #MECR]
 209
 210        mov     pc, lr
 211