LXR uboot/board/shannon/lowlevel

   1/*
   2 * Memory Setup stuff - taken from blob memsetup.S
   3 *
   4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26
  27#include <config.h>
  28#include <version.h>
  29
  30
  31/* some parameters for the board */
  32
  33MEM_BASE:       .long   0xa0000000
  34MEM_START:      .long   0xc0000000
  35
  36#define MDCNFG  0x00
  37#define MDCAS0  0x04
  38#define MDCAS1  0x08
  39#define MDCAS2  0x0c
  40#define MSC0    0x10
  41#define MSC1    0x14
  42#define MECR    0x18
  43
  44mdcas0:         .long   0xc71c703f @ cccccccf
  45mdcas1:         .long   0xffc71c71 @ fffffffc
  46mdcas2:         .long   0xffffffff @ ffffffff
  47mdcnfg:         .long   0x0334b21f @ 9326991f
  48msc0:           .long   0xfff84458 @ 42304230
  49msc1:           .long   0xffffffff @ 20182018
  50mecr:           .long   0x7fff7fff @ 01000000
  51
  52/* setting up the memory */
  53
  54.globl lowlevel_init
  55lowlevel_init:
  56        ldr     r0, MEM_BASE
  57
  58        /* Setup the flash memory */
  59        ldr     r1, msc0
  60        str     r1, [r0, #MSC0]
  61
  62        /* Set up the DRAM */
  63
  64        /* MDCAS0 */
  65        ldr     r1, mdcas0
  66        str     r1, [r0, #MDCAS0]
  67
  68        /* MDCAS1 */
  69        ldr     r1, mdcas1
  70        str     r1, [r0, #MDCAS1]
  71
  72        /* MDCAS2 */
  73        ldr     r1, mdcas2
  74        str     r1, [r0, #MDCAS2]
  75
  76        /* MDCNFG */
  77        ldr     r1, mdcnfg
  78        str     r1, [r0, #MDCNFG]
  79
  80        /* Set up PCMCIA space */
  81        ldr     r1, mecr
  82        str     r1, [r0, #MECR]
  83
  84        /* Load something to activate bank */
  85        ldr     r1, MEM_START
  86
  87.rept   8
  88        ldr     r0, [r1]
  89.endr
  90
  91        /* everything is fine now */
  92        mov     pc, lr
  93