LXR uboot/drivers/serial/serial

   1/*
   2 * SuperH SCIF device driver.
   3 * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
   4 * Copyright (C) 2002 - 2008  Paul Mundt
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19 */
  20
  21#include <common.h>
  22#include <asm/io.h>
  23#include <asm/processor.h>
  24#include "serial_sh.h"
  25
  26#if defined(CONFIG_CONS_SCIF0)
  27# define SCIF_BASE      SCIF0_BASE
  28#elif defined(CONFIG_CONS_SCIF1)
  29# define SCIF_BASE      SCIF1_BASE
  30#elif defined(CONFIG_CONS_SCIF2)
  31# define SCIF_BASE      SCIF2_BASE
  32#elif defined(CONFIG_CONS_SCIF3)
  33# define SCIF_BASE      SCIF3_BASE
  34#elif defined(CONFIG_CONS_SCIF4)
  35# define SCIF_BASE      SCIF4_BASE
  36#elif defined(CONFIG_CONS_SCIF5)
  37# define SCIF_BASE      SCIF5_BASE
  38#else
  39# error "Default SCIF doesn't set....."
  40#endif
  41
  42#if defined(CONFIG_SCIF_A)
  43        #define SCIF_BASE_PORT  PORT_SCIFA
  44#else
  45        #define SCIF_BASE_PORT  PORT_SCIF
  46#endif
  47
  48static struct uart_port sh_sci = {
  49        .membase        = (unsigned char*)SCIF_BASE,
  50        .mapbase        = SCIF_BASE,
  51        .type           = SCIF_BASE_PORT,
  52};
  53
  54void serial_setbrg(void)
  55{
  56        DECLARE_GLOBAL_DATA_PTR;
  57        sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
  58}
  59
  60int serial_init(void)
  61{
  62        sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
  63        sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
  64        sci_out(&sh_sci, SCSMR, 0);
  65        sci_out(&sh_sci, SCSMR, 0);
  66        sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
  67        sci_in(&sh_sci, SCFCR);
  68        sci_out(&sh_sci, SCFCR, 0);
  69
  70        serial_setbrg();
  71        return 0;
  72}
  73
  74#if defined(CONFIG_CPU_SH7760) || \
  75        defined(CONFIG_CPU_SH7780) || \
  76        defined(CONFIG_CPU_SH7785) || \
  77        defined(CONFIG_CPU_SH7786)
  78static int scif_rxfill(struct uart_port *port)
  79{
  80        return sci_in(port, SCRFDR) & 0xff;
  81}
  82#elif defined(CONFIG_CPU_SH7763)
  83static int scif_rxfill(struct uart_port *port)
  84{
  85        if ((port->mapbase == 0xffe00000) ||
  86                (port->mapbase == 0xffe08000)) {
  87                /* SCIF0/1*/
  88                return sci_in(port, SCRFDR) & 0xff;
  89        } else {
  90                /* SCIF2 */
  91                return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  92        }
  93}
  94#elif defined(CONFIG_ARCH_SH7372)
  95static int scif_rxfill(struct uart_port *port)
  96{
  97        if (port->type == PORT_SCIFA)
  98                return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  99        else
 100                return sci_in(port, SCRFDR);
 101}
 102#else
 103static int scif_rxfill(struct uart_port *port)
 104{
 105        return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
 106}
 107#endif
 108
 109static int serial_rx_fifo_level(void)
 110{
 111        return scif_rxfill(&sh_sci);
 112}
 113
 114void serial_raw_putc(const char c)
 115{
 116        while (1) {
 117                /* Tx fifo is empty */
 118                if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
 119                        break;
 120        }
 121
 122        sci_out(&sh_sci, SCxTDR, c);
 123        sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
 124}
 125
 126void serial_putc(const char c)
 127{
 128        if (c == '\n')
 129                serial_raw_putc('\r');
 130        serial_raw_putc(c);
 131}
 132
 133void serial_puts(const char *s)
 134{
 135        char c;
 136        while ((c = *s++) != 0)
 137                serial_putc(c);
 138}
 139
 140int serial_tstc(void)
 141{
 142        return serial_rx_fifo_level() ? 1 : 0;
 143}
 144
 145void handle_error(void)
 146{
 147        sci_in(&sh_sci, SCxSR);
 148        sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
 149        sci_in(&sh_sci, SCLSR);
 150        sci_out(&sh_sci, SCLSR, 0x00);
 151}
 152
 153int serial_getc_check(void)
 154{
 155        unsigned short status;
 156
 157        status = sci_in(&sh_sci, SCxSR);
 158
 159        if (status & SCIF_ERRORS)
 160                handle_error();
 161        if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
 162                handle_error();
 163        return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
 164}
 165
 166int serial_getc(void)
 167{
 168        unsigned short status;
 169        char ch;
 170
 171        while (!serial_getc_check())
 172                ;
 173
 174        ch = sci_in(&sh_sci, SCxRDR);
 175        status = sci_in(&sh_sci, SCxSR);
 176
 177        sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
 178
 179        if (status & SCIF_ERRORS)
 180                        handle_error();
 181
 182        if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
 183                handle_error();
 184        return ch;
 185}
 186