uboot/include/configs/IVML24.h
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   1/*
   2 * (C) Copyright 2001
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37#define CONFIG_IVML24           1       /* ...on a IVML24 board         */
  38
  39#define CONFIG_SYS_TEXT_BASE    0xFF000000
  40
  41#if defined (CONFIG_IVML24_16M)
  42# define CONFIG_IDENT_STRING     " IVML24"
  43#elif defined (CONFIG_IVML24_32M)
  44# define CONFIG_IDENT_STRING     " IVML24_128"
  45#elif defined (CONFIG_IVML24_64M)
  46# define CONFIG_IDENT_STRING     " IVML24_256"
  47#endif
  48
  49#define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  50#undef  CONFIG_8xx_CONS_SMC2
  51#undef  CONFIG_8xx_CONS_NONE
  52#define CONFIG_BAUDRATE         115200
  53
  54#define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  55#define CONFIG_8xx_GCLK_FREQ    50331648
  56
  57#define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  58
  59#define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  60
  61#if 0
  62#define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  63#else
  64#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  65#endif
  66#define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  67
  68#define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  69                                "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  70                                "nfsaddrs=10.0.0.99:10.0.0.2"
  71
  72#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73#undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  74
  75#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77#define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78
  79
  80/*
  81 * Command line configuration.
  82 */
  83#include <config_cmd_default.h>
  84
  85#define CONFIG_CMD_IDE
  86
  87
  88#define CONFIG_MAC_PARTITION
  89#define CONFIG_DOS_PARTITION
  90
  91/*
  92 * BOOTP options
  93 */
  94#define CONFIG_BOOTP_SUBNETMASK
  95#define CONFIG_BOOTP_HOSTNAME
  96#define CONFIG_BOOTP_BOOTPATH
  97#define CONFIG_BOOTP_BOOTFILESIZE
  98
  99
 100/*
 101 * Miscellaneous configurable options
 102 */
 103#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 104#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 105#if defined(CONFIG_CMD_KGDB)
 106#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 107#else
 108#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 109#endif
 110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 111#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 112#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113
 114#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 115#define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 116
 117#define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 118
 119#define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 120
 121#define CONFIG_SYS_PB_12V_ENABLE        0x00002000              /* PB 18        */
 122#define CONFIG_SYS_PB_ILOCK_SWITCH      0x00004000              /* PB 17        */
 123#define CONFIG_SYS_PB_SDRAM_CLKE        0x00008000              /* PB 16        */
 124#define CONFIG_SYS_PB_ETH_POWERDOWN     0x00010000              /* PB 15        */
 125#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000              /* PB 14        */
 126
 127#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010)        /* PC 11        */
 128#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020)        /* PC 10        */
 129
 130#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 131
 132#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 133
 134/*
 135 * Low Level Configuration Settings
 136 * (address mappings, register initial values, etc.)
 137 * You should know what you are doing if you make changes here.
 138 */
 139/*-----------------------------------------------------------------------
 140 * Internal Memory Mapped Register
 141 */
 142#define CONFIG_SYS_IMMR         0xFFF00000 /* was: 0xFF000000 */
 143
 144/*-----------------------------------------------------------------------
 145 * Definitions for initial stack pointer and data area (in DPRAM)
 146 */
 147#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 148
 149#if defined (CONFIG_IVML24_16M)
 150# define        CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 151#elif defined (CONFIG_IVML24_32M)
 152# define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 153#elif defined (CONFIG_IVML24_64M)
 154# define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 155#endif
 156
 157#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 158#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 159
 160/*-----------------------------------------------------------------------
 161 * Start addresses for the final memory configuration
 162 * (Set up by the startup code)
 163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 164 */
 165#define CONFIG_SYS_SDRAM_BASE           0x00000000
 166#define CONFIG_SYS_FLASH_BASE           0xFF000000
 167#ifdef  DEBUG
 168#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 169#else
 170#define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 171#endif
 172#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 173#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 174
 175/*
 176 * For booting Linux, the board info and command line data
 177 * have to be in the first 8 MB of memory, since this is
 178 * the maximum mapped by the Linux kernel during initialization.
 179 */
 180#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 181/*-----------------------------------------------------------------------
 182 * FLASH organization
 183 */
 184#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 185#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 186
 187#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 188#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 189
 190#define CONFIG_ENV_IS_IN_FLASH  1
 191#define CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
 192#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 193/*-----------------------------------------------------------------------
 194 * Cache Configuration
 195 */
 196#define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 197#if defined(CONFIG_CMD_KGDB)
 198#define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 199#endif
 200
 201/*-----------------------------------------------------------------------
 202 * SYPCR - System Protection Control                            11-9
 203 * SYPCR can only be written once after reset!
 204 *-----------------------------------------------------------------------
 205 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 206 */
 207#if defined(CONFIG_WATCHDOG)
 208
 209# if defined (CONFIG_IVML24_16M)
 210#  define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 211                         SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 212# elif defined (CONFIG_IVML24_32M)
 213#  define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 214                         SYPCR_SWE  | SYPCR_SWP)
 215# elif defined (CONFIG_IVML24_64M)
 216#  define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 217                         SYPCR_SWE  | SYPCR_SWP)
 218# endif
 219
 220#else
 221#define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 222#endif
 223
 224/*-----------------------------------------------------------------------
 225 * SIUMCR - SIU Module Configuration                            11-6
 226 *-----------------------------------------------------------------------
 227 * PCMCIA config., multi-function pin tri-state
 228 */
 229/* EARB, DBGC and DBPC are initialised by the HCW */
 230/* => 0x000000C0 */
 231#define CONFIG_SYS_SIUMCR       (SIUMCR_BSC | SIUMCR_GB5E)
 232
 233/*-----------------------------------------------------------------------
 234 * TBSCR - Time Base Status and Control                         11-26
 235 *-----------------------------------------------------------------------
 236 * Clear Reference Interrupt Status, Timebase freezing enabled
 237 */
 238#define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 239
 240/*-----------------------------------------------------------------------
 241 * PISCR - Periodic Interrupt Status and Control                11-31
 242 *-----------------------------------------------------------------------
 243 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 244 */
 245#define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 246
 247/*-----------------------------------------------------------------------
 248 * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 249 *-----------------------------------------------------------------------
 250 * Reset PLL lock status sticky bit, timer expired status bit and timer
 251 * interrupt status bit, set PLL multiplication factor !
 252 */
 253/* 0x00B0C0C0 */
 254#define CONFIG_SYS_PLPRCR                                                       \
 255                (       (11 << PLPRCR_MF_SHIFT) |                       \
 256                        PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 257                        /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 258                        PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 259                )
 260
 261/*-----------------------------------------------------------------------
 262 * SCCR - System Clock and reset Control Register               15-27
 263 *-----------------------------------------------------------------------
 264 * Set clock output, timebase and RTC source and divider,
 265 * power management and some other internal clocks
 266 */
 267#define SCCR_MASK       SCCR_EBDF11
 268/* 0x01800014 */
 269#define CONFIG_SYS_SCCR (SCCR_COM01     | /*SCCR_TBS|*/         \
 270                         SCCR_RTDIV     |   SCCR_RTSEL    |     \
 271                         /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 272                         SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 273                         SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 274                         SCCR_DFNH000   |   SCCR_DFLCD101 |     \
 275                         SCCR_DFALCD00)
 276
 277/*-----------------------------------------------------------------------
 278 * RTCSC - Real-Time Clock Status and Control Register          11-27
 279 *-----------------------------------------------------------------------
 280 */
 281/* 0x00C3 */
 282#define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 283
 284
 285/*-----------------------------------------------------------------------
 286 * RCCR - RISC Controller Configuration Register                19-4
 287 *-----------------------------------------------------------------------
 288 */
 289/* TIMEP=2 */
 290#define CONFIG_SYS_RCCR 0x0200
 291
 292/*-----------------------------------------------------------------------
 293 * RMDS - RISC Microcode Development Support Control Register
 294 *-----------------------------------------------------------------------
 295 */
 296#define CONFIG_SYS_RMDS 0
 297
 298/*-----------------------------------------------------------------------
 299 *
 300 * Interrupt Levels
 301 *-----------------------------------------------------------------------
 302 */
 303#define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 304
 305/*-----------------------------------------------------------------------
 306 * PCMCIA stuff
 307 *-----------------------------------------------------------------------
 308 *
 309 */
 310#define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 311#define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 312#define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 313#define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 314#define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 315#define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 316#define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 317#define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 318
 319/*-----------------------------------------------------------------------
 320 * IDE/ATA stuff
 321 *-----------------------------------------------------------------------
 322 */
 323#define CONFIG_IDE_8xx_DIRECT   1       /* PCMCIA interface required    */
 324#define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 325
 326#define CONFIG_SYS_IDE_MAXBUS           1       /* The IVML24 has only 1 IDE bus*/
 327#define CONFIG_SYS_IDE_MAXDEVICE        1       /*    ... and only 1 IDE device */
 328
 329#define CONFIG_SYS_ATA_BASE_ADDR        0xFE100000
 330#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 331#undef  CONFIG_SYS_ATA_IDE1_OFFSET              /* only one IDE bus available   */
 332
 333#define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 334#define CONFIG_SYS_ATA_REG_OFFSET       0x0080  /* Offset for normal register accesses  */
 335#define CONFIG_SYS_ATA_ALT_OFFSET       0x0100  /* Offset for alternate registers       */
 336
 337/*-----------------------------------------------------------------------
 338 *
 339 *-----------------------------------------------------------------------
 340 *
 341 */
 342#define CONFIG_SYS_DER  0
 343
 344/*
 345 * Init Memory Controller:
 346 *
 347 * BR0 and OR0 (FLASH)
 348 */
 349
 350#define FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank #0        */
 351
 352/* used to re-map FLASH both when starting from SRAM or FLASH:
 353 * restrict access enough to keep SRAM working (if any)
 354 * but not too much to meddle with FLASH accesses
 355 */
 356/* EPROMs are 512kb */
 357#define CONFIG_SYS_REMAP_OR_AM          0xFFF80000      /* OR addr mask */
 358#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 359
 360/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 361#define CONFIG_SYS_OR_TIMING_FLASH      (OR_SCY_5_CLK | OR_EHTR)
 362
 363#define CONFIG_SYS_OR0_REMAP    ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
 364                                CONFIG_SYS_OR_TIMING_FLASH)
 365#define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
 366                                CONFIG_SYS_OR_TIMING_FLASH)
 367/* 16 bit, bank valid */
 368#define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 369
 370/*
 371 * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 372 *
 373 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 374 */
 375#define ELIC_SACCO_BASE         0xFE000000
 376#define ELIC_SACCO_OR_AM        0xFFFF8000
 377#define ELIC_SACCO_TIMING       (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
 378
 379#define CONFIG_SYS_OR1  (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
 380                        ELIC_SACCO_TIMING)
 381#define CONFIG_SYS_BR1  ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 382
 383/*
 384 * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 385 *
 386 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 387 */
 388#define ELIC_EPIC_BASE          0xFE008000
 389#define ELIC_EPIC_OR_AM         0xFFFF8000
 390#define ELIC_EPIC_TIMING        (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
 391
 392#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
 393                        ELIC_EPIC_TIMING)
 394#define CONFIG_SYS_BR2  ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 395
 396/*
 397 * BR3/OR3: SDRAM
 398 *
 399 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 400 */
 401#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 402#define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 403#define SDRAM_TIMING            OR_SCY_0_CLK    /* SDRAM-Timing */
 404
 405#define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 406
 407#define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
 408#define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 409
 410/*
 411 * BR4/OR4 - HDLC Address
 412 *
 413 *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
 414 */
 415#define HDLC_ADDR_BASE          0xFE108000      /* HDLC Address area */
 416#define HDLC_ADDR_OR_AM         0xFFFF8000
 417#define HDLC_ADDR_TIMING        OR_SCY_1_CLK
 418
 419#define CONFIG_SYS_OR4  (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
 420#define CONFIG_SYS_BR4  ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
 421
 422/*
 423 * BR5/OR5: SHARC ADSP-2165L
 424 *
 425 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 426 */
 427#define SHARC_BASE              0xFE400000
 428#define SHARC_OR_AM             0xFFC00000
 429#define SHARC_TIMING            OR_SCY_0_CLK
 430
 431#define CONFIG_SYS_OR5  (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
 432#define CONFIG_SYS_BR5  ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 433
 434/*
 435 * Memory Periodic Timer Prescaler
 436 */
 437
 438/* periodic timer for refresh */
 439#define CONFIG_SYS_MBMR_PTB     204
 440
 441/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 442#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 443#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 444
 445/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 446#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 447
 448#if defined (CONFIG_IVML24_16M)
 449# define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 450#elif defined (CONFIG_IVML24_32M)
 451# define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 452#elif defined (CONFIG_IVML24_64M)
 453# define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV8          /* setting for 1 bank   */
 454#endif
 455
 456
 457/*
 458 * MBMR settings for SDRAM
 459 */
 460
 461#if defined (CONFIG_IVML24_16M)
 462 /* 8 column SDRAM */
 463# define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 464                         MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 465                         MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 466#elif defined (CONFIG_IVML24_32M)
 467/* 128 MBit SDRAM */
 468# define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 469                         MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 470                         MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 471#elif defined (CONFIG_IVML24_64M)
 472/* 128 MBit SDRAM */
 473# define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 474                         MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 475                         MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 476#endif
 477#endif  /* __CONFIG_H */
 478