1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32
33#define CONFIG_BOOKE 1
34#define CONFIG_E500 1
35#define CONFIG_MPC85xx 1
36#define CONFIG_CPM2 1
37#define CONFIG_MPC8541 1
38#define CONFIG_MPC8541CDS 1
39
40#define CONFIG_SYS_TEXT_BASE 0xfff80000
41
42#define CONFIG_PCI
43#define CONFIG_SYS_PCI_64BIT 1
44#define CONFIG_TSEC_ENET
45#define CONFIG_ENV_OVERWRITE
46
47#define CONFIG_FSL_LAW 1
48
49#define CONFIG_FSL_VIA
50
51#ifndef __ASSEMBLY__
52extern unsigned long get_clock_freq(void);
53#endif
54#define CONFIG_SYS_CLK_FREQ get_clock_freq()
55
56
57
58
59#define CONFIG_L2_CACHE
60#define CONFIG_BTB
61
62#define CONFIG_SYS_MEMTEST_START 0x00200000
63#define CONFIG_SYS_MEMTEST_END 0x00400000
64
65
66
67
68
69#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
70#define CONFIG_SYS_CCSRBAR 0xe0000000
71#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
72#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
73
74
75#define CONFIG_FSL_DDR1
76#define CONFIG_SPD_EEPROM
77#define CONFIG_DDR_SPD
78#undef CONFIG_FSL_DDR_INTERACTIVE
79
80#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81
82#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
84
85#define CONFIG_NUM_DDR_CONTROLLERS 1
86#define CONFIG_DIMM_SLOTS_PER_CTLR 1
87#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
88
89
90#define SPD_EEPROM_ADDRESS 0x51
91
92
93
94
95#ifndef CONFIG_SPD_EEPROM
96#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
97#endif
98
99#undef CONFIG_CLOCKS_IN_MHZ
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135#define CONFIG_SYS_FLASH_BASE 0xff000000
136
137#define CONFIG_SYS_BR0_PRELIM 0xff801001
138#define CONFIG_SYS_BR1_PRELIM 0xff001001
139
140#define CONFIG_SYS_OR0_PRELIM 0xff806e65
141#define CONFIG_SYS_OR1_PRELIM 0xff806e65
142
143#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
144#define CONFIG_SYS_MAX_FLASH_BANKS 2
145#define CONFIG_SYS_MAX_FLASH_SECT 128
146#undef CONFIG_SYS_FLASH_CHECKSUM
147#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
148#define CONFIG_SYS_FLASH_WRITE_TOUT 500
149
150#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
151
152#define CONFIG_FLASH_CFI_DRIVER
153#define CONFIG_SYS_FLASH_CFI
154#define CONFIG_SYS_FLASH_EMPTY_INFO
155
156
157
158
159
160#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
161#define CONFIG_SYS_LBC_SDRAM_SIZE 64
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181#define CONFIG_SYS_BR2_PRELIM 0xf0001861
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197#define CONFIG_SYS_OR2_PRELIM 0xfc006901
198
199#define CONFIG_SYS_LBC_LCRR 0x00030004
200#define CONFIG_SYS_LBC_LBCR 0x00000000
201#define CONFIG_SYS_LBC_LSRT 0x20000000
202#define CONFIG_SYS_LBC_MRTPR 0x00000000
203
204
205
206
207
208
209
210#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
211 | LSDMR_PRETOACT7 \
212 | LSDMR_ACTTORW7 \
213 | LSDMR_BL8 \
214 | LSDMR_WRC4 \
215 | LSDMR_CL3 \
216 | LSDMR_RFEN \
217 )
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249#define CONFIG_FSL_CADMUS
250
251#define CADMUS_BASE_ADDR 0xf8000000
252#define CONFIG_SYS_BR3_PRELIM 0xf8000801
253#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
254
255#define CONFIG_SYS_INIT_RAM_LOCK 1
256#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
257#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
258
259#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
260#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
261
262#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
263#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
264
265
266#define CONFIG_CONS_INDEX 2
267#define CONFIG_SYS_NS16550
268#define CONFIG_SYS_NS16550_SERIAL
269#define CONFIG_SYS_NS16550_REG_SIZE 1
270#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
271
272#define CONFIG_SYS_BAUDRATE_TABLE \
273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
274
275#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
276#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
277
278
279#define CONFIG_SYS_HUSH_PARSER
280#ifdef CONFIG_SYS_HUSH_PARSER
281#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
282#endif
283
284
285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
287#define CONFIG_OF_STDOUT_VIA_ALIAS 1
288
289
290
291
292#define CONFIG_FSL_I2C
293#define CONFIG_HARD_I2C
294#undef CONFIG_SOFT_I2C
295#define CONFIG_SYS_I2C_SPEED 400000
296#define CONFIG_SYS_I2C_SLAVE 0x7F
297#define CONFIG_SYS_I2C_NOPROBES {0x69}
298#define CONFIG_SYS_I2C_OFFSET 0x3000
299
300
301#define CONFIG_ID_EEPROM
302#define CONFIG_SYS_I2C_EEPROM_CCID
303#define CONFIG_SYS_ID_EEPROM
304#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
305#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
306
307
308
309
310
311#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
312#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
313#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
314#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
315#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
316#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
317#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
318#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
319
320#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
321#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
322#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
323#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000
324#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
325#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
326#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
327#define CONFIG_SYS_PCI2_IO_SIZE 0x100000
328
329#ifdef CONFIG_LEGACY
330#define BRIDGE_ID 17
331#define VIA_ID 2
332#else
333#define BRIDGE_ID 28
334#define VIA_ID 4
335#endif
336
337#if defined(CONFIG_PCI)
338
339#define CONFIG_MPC85XX_PCI2
340#define CONFIG_NET_MULTI
341#define CONFIG_PCI_PNP
342
343#undef CONFIG_EEPRO100
344#undef CONFIG_TULIP
345
346#undef CONFIG_PCI_SCAN_SHOW
347#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
348
349#endif
350
351
352#if defined(CONFIG_TSEC_ENET)
353
354#ifndef CONFIG_NET_MULTI
355#define CONFIG_NET_MULTI 1
356#endif
357
358#define CONFIG_MII 1
359#define CONFIG_TSEC1 1
360#define CONFIG_TSEC1_NAME "TSEC0"
361#define CONFIG_TSEC2 1
362#define CONFIG_TSEC2_NAME "TSEC1"
363#define TSEC1_PHY_ADDR 0
364#define TSEC2_PHY_ADDR 1
365#define TSEC1_PHYIDX 0
366#define TSEC2_PHYIDX 0
367#define TSEC1_FLAGS TSEC_GIGABIT
368#define TSEC2_FLAGS TSEC_GIGABIT
369
370
371#define CONFIG_ETHPRIME "TSEC0"
372
373#endif
374
375
376
377
378#define CONFIG_ENV_IS_IN_FLASH 1
379#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
380#define CONFIG_ENV_SECT_SIZE 0x40000
381#define CONFIG_ENV_SIZE 0x2000
382
383#define CONFIG_LOADS_ECHO 1
384#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
385
386
387
388
389#define CONFIG_BOOTP_BOOTFILESIZE
390#define CONFIG_BOOTP_BOOTPATH
391#define CONFIG_BOOTP_GATEWAY
392#define CONFIG_BOOTP_HOSTNAME
393
394
395
396
397
398#include <config_cmd_default.h>
399
400#define CONFIG_CMD_PING
401#define CONFIG_CMD_I2C
402#define CONFIG_CMD_MII
403#define CONFIG_CMD_ELF
404#define CONFIG_CMD_IRQ
405#define CONFIG_CMD_SETEXPR
406#define CONFIG_CMD_REGINFO
407
408#if defined(CONFIG_PCI)
409 #define CONFIG_CMD_PCI
410#endif
411
412
413#undef CONFIG_WATCHDOG
414
415
416
417
418#define CONFIG_SYS_LONGHELP
419#define CONFIG_CMDLINE_EDITING
420#define CONFIG_AUTO_COMPLETE
421#define CONFIG_SYS_LOAD_ADDR 0x2000000
422#define CONFIG_SYS_PROMPT "=> "
423#if defined(CONFIG_CMD_KGDB)
424#define CONFIG_SYS_CBSIZE 1024
425#else
426#define CONFIG_SYS_CBSIZE 256
427#endif
428#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
429#define CONFIG_SYS_MAXARGS 16
430#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
431#define CONFIG_SYS_HZ 1000
432
433
434
435
436
437
438#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
439#define CONFIG_SYS_BOOTM_LEN (64 << 20)
440
441#if defined(CONFIG_CMD_KGDB)
442#define CONFIG_KGDB_BAUDRATE 230400
443#define CONFIG_KGDB_SER_INDEX 2
444#endif
445
446
447
448
449
450
451#if defined(CONFIG_TSEC_ENET)
452#define CONFIG_HAS_ETH0
453#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
454#define CONFIG_HAS_ETH1
455#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
456#define CONFIG_HAS_ETH2
457#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
458#endif
459
460#define CONFIG_IPADDR 192.168.1.253
461
462#define CONFIG_HOSTNAME unknown
463#define CONFIG_ROOTPATH /nfsroot
464#define CONFIG_BOOTFILE your.uImage
465
466#define CONFIG_SERVERIP 192.168.1.1
467#define CONFIG_GATEWAYIP 192.168.1.1
468#define CONFIG_NETMASK 255.255.255.0
469
470#define CONFIG_LOADADDR 200000
471
472#define CONFIG_BOOTDELAY 10
473#undef CONFIG_BOOTARGS
474
475#define CONFIG_BAUDRATE 115200
476
477#define CONFIG_EXTRA_ENV_SETTINGS \
478 "netdev=eth0\0" \
479 "consoledev=ttyS1\0" \
480 "ramdiskaddr=600000\0" \
481 "ramdiskfile=your.ramdisk.u-boot\0" \
482 "fdtaddr=400000\0" \
483 "fdtfile=your.fdt.dtb\0"
484
485#define CONFIG_NFSBOOTCOMMAND \
486 "setenv bootargs root=/dev/nfs rw " \
487 "nfsroot=$serverip:$rootpath " \
488 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
489 "console=$consoledev,$baudrate $othbootargs;" \
490 "tftp $loadaddr $bootfile;" \
491 "tftp $fdtaddr $fdtfile;" \
492 "bootm $loadaddr - $fdtaddr"
493
494#define CONFIG_RAMBOOTCOMMAND \
495 "setenv bootargs root=/dev/ram rw " \
496 "console=$consoledev,$baudrate $othbootargs;" \
497 "tftp $ramdiskaddr $ramdiskfile;" \
498 "tftp $loadaddr $bootfile;" \
499 "bootm $loadaddr $ramdiskaddr"
500
501#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
502
503#endif
504