1/* 2 * (C) Copyright 2001 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2001 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27/* 28 * board/config.h - configuration options, board specific 29 */ 30 31#ifndef __CONFIG_H 32#define __CONFIG_H 33 34/* 35 * High Level Configuration Options 36 * (easy to change) 37 */ 38 39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 40#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ 41 42#define CONFIG_SYS_TEXT_BASE 0x40000000 43 44/*#define CONFIG_VIDEO 1 */ 45 46#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED 47#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 48#undef CONFIG_8xx_CONS_SMC2 49#undef CONFIG_8xx_CONS_NONE 50#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ 51#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 52#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ 53 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ 54 "nfsaddrs=10.77.77.20:10.77.77.250" 55#define CONFIG_BOOTCOMMAND "bootm 400e0000" 56 57#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 58#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 59#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ 60#define CONFIG_SOURCE 61 62/* 63 * BOOTP options 64 */ 65#define CONFIG_BOOTP_SUBNETMASK 66#define CONFIG_BOOTP_GATEWAY 67#define CONFIG_BOOTP_HOSTNAME 68#define CONFIG_BOOTP_BOOTPATH 69#define CONFIG_BOOTP_BOOTFILESIZE 70 71 72/* 73 * Command line configuration. 74 */ 75#include <config_cmd_default.h> 76 77#define CONFIG_CMD_SOURCE 78 79 80/* call various generic functions */ 81#define CONFIG_MISC_INIT_R 82 83/* 84 * Miscellaneous configurable options 85 */ 86#define CONFIG_SYS_LONGHELP /* undef to save memory */ 87#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 88#if defined(CONFIG_CMD_KGDB) 89#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 90#else 91#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 92#endif 93#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 94#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 95#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 96 97#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 98#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 99 100#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 101 102#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 103 104#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 105 106/* 107 * Low Level Configuration Settings 108 * (address mappings, register initial values, etc.) 109 * You should know what you are doing if you make changes here. 110 */ 111/*----------------------------------------------------------------------- 112 * Internal Memory Mapped Register 113 */ 114#define CONFIG_SYS_IMMR 0xFFF00000 115 116/*----------------------------------------------------------------------- 117 * Definitions for initial stack pointer and data area (in DPRAM) 118 */ 119#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 120#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 121#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 122#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 123 124/*----------------------------------------------------------------------- 125 * Start addresses for the final memory configuration 126 * (Set up by the startup code) 127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 128 */ 129#define CONFIG_SYS_SDRAM_BASE 0x00000000 130#define CONFIG_SYS_FLASH_BASE 0x40000000 131#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 132#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 133#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 134 135/* 136 * For booting Linux, the board info and command line data 137 * have to be in the first 8 MB of memory, since this is 138 * the maximum mapped by the Linux kernel during initialization. 139 */ 140#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 141 142/*----------------------------------------------------------------------- 143 * FLASH organization 144 */ 145#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 146#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 147 148#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 150 151#define CONFIG_ENV_IS_IN_FLASH 1 152#define xEMBED 153#ifdef EMBED 154#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ 155#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE 156#else 157#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */ 158#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ 159#endif 160 161#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ 162#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ 163#define CONFIG_SYS_FLASH_SN_BYTES 8 164 165/*----------------------------------------------------------------------- 166 * Cache Configuration 167 */ 168#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 169#if defined(CONFIG_CMD_KGDB) 170#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 171#endif 172 173/*----------------------------------------------------------------------- 174 * SYPCR - System Protection Control 11-9 175 * SYPCR can only be written once after reset! 176 *----------------------------------------------------------------------- 177 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 178 */ 179#if defined(CONFIG_WATCHDOG) 180#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 181 SYPCR_SWE | SYPCR_SWP) 182#else 183#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 184#endif 185 186/*----------------------------------------------------------------------- 187 * SIUMCR - SIU Module Configuration 12-30 188 *----------------------------------------------------------------------- 189 * PCMCIA config., multi-function pin tri-state 190 */ 191#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) 192 193/*----------------------------------------------------------------------- 194 * TBSCR - Time Base Status and Control 12-16 195 *----------------------------------------------------------------------- 196 * Clear Reference Interrupt Status, Timebase freezing enabled 197 */ 198#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 199 200/*----------------------------------------------------------------------- 201 * RTCSC - Real-Time Clock Status and Control Register 12-18 202 *----------------------------------------------------------------------- 203 */ 204#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 205 206/*----------------------------------------------------------------------- 207 * PISCR - Periodic Interrupt Status and Control 12-23 208 *----------------------------------------------------------------------- 209 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 210 */ 211#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 212 213/*----------------------------------------------------------------------- 214 * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 215 *----------------------------------------------------------------------- 216 * Reset PLL lock status sticky bit, timer expired status bit and timer 217 * interrupt status bit 218 */ 219#define MPC8XX_SPEED 66666666L 220#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ 221#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) 222#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) 223#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) 224 225/*----------------------------------------------------------------------- 226 * SCCR - System Clock and reset Control Register 5-3 227 *----------------------------------------------------------------------- 228 * Set clock output, timebase and RTC source and divider, 229 * power management and some other internal clocks 230 */ 231#define SCCR_MASK SCCR_EBDF11 232#define CONFIG_SYS_SCCR (SCCR_TBS | \ 233 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 234 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 235 SCCR_DFALCD00) 236 237/*----------------------------------------------------------------------- 238 * 239 *----------------------------------------------------------------------- 240 * 241 */ 242#define CONFIG_SYS_DER 0 243 244/* 245 * Init Memory Controller: 246 * 247 * BR0 and OR0 (FLASH) 248 */ 249 250#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 251 252/* used to re-map FLASH both when starting from SRAM or FLASH: 253 * restrict access enough to keep SRAM working (if any) 254 * but not too much to meddle with FLASH accesses 255 */ 256#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 257#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 258 259/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ 260#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ 261 OR_SCY_8_CLK ) 262 263#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 264#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 265#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 266 267/* 268 * BR1/2 and OR1/2 (SDRAM) 269 */ 270#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ 271#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ 272#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 273 274/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ 275#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) 276 277#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 278#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 279#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM 280#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 281 282/* IO and memory mapped stuff */ 283#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ 284#define NX823_IO_BASE 0xFF000000 /* start of IO */ 285#define GPOUT_OFFSET (3<<16) 286#define QUART_OFFSET (4<<16) 287#define VIDAC_OFFSET (5<<16) 288#define CPLD_OFFSET (6<<16) 289#define SED1386_OFFSET (7<<16) 290 291/* 292 * BR3 and OR3 (general purpose output latches) 293 */ 294#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) 295#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) 296#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) 297#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V) 298 299/* 300 * BR4 and OR4 (QUART) 301 */ 302#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) 303#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) 304#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) 305#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) 306 307/* 308 * BR5 and OR5 (Video DAC) 309 */ 310#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) 311#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) 312#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) 313#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) 314 315/* 316 * BR6 and OR6 (CPLD) 317 * FIXME timing not verified for CPLD 318 */ 319#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) 320#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) 321#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) 322#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) 323 324/* 325 * BR7 and OR7 (SED1386) 326 * FIXME timing not verified for SED controller 327 */ 328#define SED1386_BASE 0xF7000000 329#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) 330#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) 331 332/* 333 * Memory Periodic Timer Prescaler 334 */ 335 336/* periodic timer for refresh */ 337#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 338 339/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 340#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 341#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 342 343/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 344#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 345#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 346 347/* 348 * MAMR settings for SDRAM 349 */ 350 351/* 8 column SDRAM */ 352#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 353 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 354 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 355/* 9 column SDRAM */ 356#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 357 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 358 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 359 360#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ 361#define CONFIG_ETHADDR 00:10:20:30:40:50 362#define CONFIG_IPADDR 10.77.77.20 363#define CONFIG_SERVERIP 10.77.77.250 364 365#endif /* __CONFIG_H */ 366