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31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34
35
36
37
38#define CONFIG_405GP 1
39#define CONFIG_4xx 1
40#define CONFIG_PCI405 1
41
42#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
43
44#define CONFIG_BOARD_EARLY_INIT_F 1
45#define CONFIG_MISC_INIT_R 1
46
47#define CONFIG_SYS_CLK_FREQ 25000000
48
49#define CONFIG_BOARD_TYPES 1
50
51#define CONFIG_BAUDRATE 115200
52#define CONFIG_BOOTDELAY 0
53
54#undef CONFIG_BOOTARGS
55#define CONFIG_EXTRA_ENV_SETTINGS \
56 "mem_linux=14336k\0" \
57 "optargs=panic=0\0" \
58 "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
59 "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
60 ""
61#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
62
63#define CONFIG_PREBOOT
64
65
66
67
68#include <config_cmd_default.h>
69
70#undef CONFIG_CMD_IMLS
71#undef CONFIG_CMD_ITEST
72#undef CONFIG_CMD_LOADB
73#undef CONFIG_CMD_LOADS
74#undef CONFIG_CMD_NET
75#undef CONFIG_CMD_NFS
76
77#define CONFIG_CMD_PCI
78#define CONFIG_CMD_ELF
79#define CONFIG_CMD_I2C
80#define CONFIG_CMD_BSP
81#define CONFIG_CMD_EEPROM
82
83#undef CONFIG_WATCHDOG
84
85#define CONFIG_SDRAM_BANK0 1
86
87#define CONFIG_PRAM 2048
88
89
90
91
92#define CONFIG_SYS_PROMPT "=> "
93
94#define CONFIG_SYS_HUSH_PARSER
95#ifdef CONFIG_SYS_HUSH_PARSER
96#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
97#endif
98
99#if defined(CONFIG_CMD_KGDB)
100#define CONFIG_SYS_CBSIZE 1024
101#else
102#define CONFIG_SYS_CBSIZE 256
103#endif
104#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
105#define CONFIG_SYS_MAXARGS 16
106#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
107
108#define CONFIG_SYS_DEVICE_NULLDEV 1
109
110#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
111
112#define CONFIG_SYS_MEMTEST_START 0x0400000
113#define CONFIG_SYS_MEMTEST_END 0x0C00000
114
115#define CONFIG_CONS_INDEX 1
116#define CONFIG_SYS_NS16550
117#define CONFIG_SYS_NS16550_SERIAL
118#define CONFIG_SYS_NS16550_REG_SIZE 1
119#define CONFIG_SYS_NS16550_CLK get_serial_clock()
120
121#undef CONFIG_SYS_EXT_SERIAL_CLOCK
122#define CONFIG_SYS_BASE_BAUD 691200
123
124
125#define CONFIG_SYS_BAUDRATE_TABLE \
126 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
127 57600, 115200, 230400, 460800, 921600 }
128
129#define CONFIG_SYS_LOAD_ADDR 0x100000
130#define CONFIG_SYS_EXTBDINFO 1
131
132#define CONFIG_SYS_HZ 1000
133
134#undef CONFIG_ZERO_BOOTDELAY_CHECK
135
136#define CONFIG_VERSION_VARIABLE 1
137
138
139
140
141
142#define PCI_HOST_ADAPTER 0
143#define PCI_HOST_FORCE 1
144#define PCI_HOST_AUTO 2
145
146#define CONFIG_PCI
147#define CONFIG_PCI_HOST PCI_HOST_ADAPTER
148#undef CONFIG_PCI_PNP
149
150
151#define CONFIG_PCI_SCAN_SHOW
152
153#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
154#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407
155#define CONFIG_SYS_PCI_CLASSCODE 0x0280
156#define CONFIG_SYS_PCI_PTM1LA 0x00000000
157#define CONFIG_SYS_PCI_PTM1MS 0xff000001
158#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
159
160#define CONFIG_SYS_PCI_PTM2LA 0xef600000
161#define CONFIG_SYS_PCI_PTM2MS 0xffe00001
162#define CONFIG_SYS_PCI_PTM2PCI 0x00000000
163
164
165
166
167
168
169#define CONFIG_SYS_SDRAM_BASE 0x00000000
170#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172#define CONFIG_SYS_MONITOR_LEN (192 * 1024)
173#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
174
175
176
177
178
179
180#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
181
182
183
184#define CONFIG_SYS_MAX_FLASH_BANKS 1
185#define CONFIG_SYS_MAX_FLASH_SECT 256
186
187#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
188#define CONFIG_SYS_FLASH_WRITE_TOUT 500
189
190#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
191#define CONFIG_SYS_FLASH_ADDR0 0x5555
192#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
193
194
195
196
197#define CONFIG_SYS_FLASH_READ0 0x0000
198#define CONFIG_SYS_FLASH_READ1 0x0001
199#define CONFIG_SYS_FLASH_READ2 0x0002
200
201#define CONFIG_SYS_FLASH_EMPTY_INFO
202
203#define CONFIG_ENV_IS_IN_EEPROM 1
204#define CONFIG_ENV_OFFSET 0x000
205#define CONFIG_ENV_SIZE 0x400
206
207
208#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
209#define CONFIG_SYS_NVRAM_SIZE (32*1024)
210
211
212
213
214#define CONFIG_HARD_I2C
215#define CONFIG_PPC4XX_I2C
216#define CONFIG_SYS_I2C_SPEED 400000
217#define CONFIG_SYS_I2C_SLAVE 0x7F
218
219#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
220#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
221
222#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
223#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
224
225
226#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
227
228
229
230
231
232
233
234#define FLASH_BASE0_PRELIM 0xFFE00000
235
236
237
238
239
240
241#define CONFIG_SYS_EBC_PB0AP 0x92015480
242#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
243
244
245#define CONFIG_SYS_EBC_PB1AP 0x01005280
246#define CONFIG_SYS_EBC_PB1CR 0xF0218000
247
248
249#define CONFIG_SYS_EBC_PB2AP 0x010053C0
250
251#define CONFIG_SYS_EBC_PB2CR 0xF0018000
252
253
254#define CONFIG_SYS_EBC_PB3AP 0x010053C0
255#define CONFIG_SYS_EBC_PB3CR 0xF041C000
256#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
257
258
259
260
261
262#define CONFIG_SYS_FPGA_MODE 0x00
263#define CONFIG_SYS_FPGA_STATUS 0x02
264#define CONFIG_SYS_FPGA_TS 0x04
265#define CONFIG_SYS_FPGA_TS_LOW 0x06
266#define CONFIG_SYS_FPGA_TS_CAP0 0x10
267#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
268#define CONFIG_SYS_FPGA_TS_CAP1 0x14
269#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
270#define CONFIG_SYS_FPGA_TS_CAP2 0x18
271#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
272#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
273#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
274
275
276#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
277#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
278#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
279#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
280
281
282#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
283#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
284#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
285#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
286#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
287
288#define CONFIG_SYS_FPGA_SPARTAN2 1
289#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
290
291
292#define CONFIG_SYS_FPGA_PRG 0x04000000
293#define CONFIG_SYS_FPGA_CLK 0x02000000
294#define CONFIG_SYS_FPGA_DATA 0x01000000
295#define CONFIG_SYS_FPGA_INIT 0x00400000
296#define CONFIG_SYS_FPGA_DONE 0x00800000
297
298#define CONFIG_SYS_FPGA_INIT_V12 0x00008000
299#define CONFIG_SYS_FPGA_DONE_V12 0x00010000
300
301
302
303
304
305#define CONFIG_SYS_TEMP_STACK_OCM 1
306
307#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
308#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
309#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
310#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
311
312#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
313#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
314
315#endif
316