1/* 2 * Copyright (C) 2006 Atmel Corporation 3 * 4 * Configuration settings for the AVR32 Network Gateway 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27#include <asm/arch/hardware.h> 28 29#define CONFIG_AVR32 30#define CONFIG_AT32AP 31#define CONFIG_AT32AP7000 32#define CONFIG_ATNGW100 33 34#define CONFIG_SYS_HZ 1000 35 36/* 37 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 38 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency 39 * and the PBA bus to run at 1/4 the PLL frequency. 40 */ 41#define CONFIG_PLL 42#define CONFIG_SYS_POWER_MANAGER 43#define CONFIG_SYS_OSC0_HZ 20000000 44#define CONFIG_SYS_PLL0_DIV 1 45#define CONFIG_SYS_PLL0_MUL 7 46#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 47#define CONFIG_SYS_CLKDIV_CPU 0 48#define CONFIG_SYS_CLKDIV_HSB 1 49#define CONFIG_SYS_CLKDIV_PBA 2 50#define CONFIG_SYS_CLKDIV_PBB 1 51 52/* Reserve VM regions for SDRAM and NOR flash */ 53#define CONFIG_SYS_NR_VM_REGIONS 2 54 55/* 56 * The PLLOPT register controls the PLL like this: 57 * icp = PLLOPT<2> 58 * ivco = PLLOPT<1:0> 59 * 60 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 61 */ 62#define CONFIG_SYS_PLL0_OPT 0x04 63 64#define CONFIG_USART_BASE ATMEL_BASE_USART1 65#define CONFIG_USART_ID 1 66/* User serviceable stuff */ 67#define CONFIG_DOS_PARTITION 68 69#define CONFIG_CMDLINE_TAG 70#define CONFIG_SETUP_MEMORY_TAGS 71#define CONFIG_INITRD_TAG 72 73#define CONFIG_STACKSIZE (2048) 74 75#define CONFIG_BAUDRATE 115200 76#define CONFIG_BOOTARGS \ 77 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" 78#define CONFIG_BOOTCOMMAND \ 79 "fsload; bootm" 80 81/* 82 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage 83 * data on the serial line may interrupt the boot sequence. 84 */ 85#define CONFIG_BOOTDELAY 1 86#define CONFIG_AUTOBOOT 87#define CONFIG_AUTOBOOT_KEYED 88#define CONFIG_AUTOBOOT_PROMPT \ 89 "Press SPACE to abort autoboot in %d seconds\n", bootdelay 90#define CONFIG_AUTOBOOT_DELAY_STR "d" 91#define CONFIG_AUTOBOOT_STOP_STR " " 92 93/* 94 * After booting the board for the first time, new ethernet addresses 95 * should be generated and assigned to the environment variables 96 * "ethaddr" and "eth1addr". This is normally done during production. 97 */ 98#define CONFIG_OVERWRITE_ETHADDR_ONCE 99#define CONFIG_NET_MULTI 100 101/* 102 * BOOTP/DHCP options 103 */ 104#define CONFIG_BOOTP_SUBNETMASK 105#define CONFIG_BOOTP_GATEWAY 106 107/* 108 * Command line configuration. 109 */ 110#include <config_cmd_default.h> 111 112#define CONFIG_CMD_ASKENV 113#define CONFIG_CMD_DHCP 114#define CONFIG_CMD_EXT2 115#define CONFIG_CMD_FAT 116#define CONFIG_CMD_JFFS2 117#define CONFIG_CMD_MMC 118#define CONFIG_CMD_SF 119#define CONFIG_CMD_SPI 120 121#undef CONFIG_CMD_FPGA 122#undef CONFIG_CMD_SETGETDCR 123#undef CONFIG_CMD_SOURCE 124#undef CONFIG_CMD_XIMG 125 126#define CONFIG_ATMEL_USART 127#define CONFIG_MACB 128#define CONFIG_PORTMUX_PIO 129#define CONFIG_SYS_NR_PIOS 5 130#define CONFIG_SYS_HSDRAMC 131#define CONFIG_MMC 132#define CONFIG_ATMEL_MCI 133#define CONFIG_ATMEL_SPI 134 135#define CONFIG_SPI_FLASH 136#define CONFIG_SPI_FLASH_ATMEL 137 138#define CONFIG_SYS_DCACHE_LINESZ 32 139#define CONFIG_SYS_ICACHE_LINESZ 32 140 141#define CONFIG_NR_DRAM_BANKS 1 142 143#define CONFIG_SYS_FLASH_CFI 144#define CONFIG_FLASH_CFI_DRIVER 145 146#define CONFIG_SYS_FLASH_BASE 0x00000000 147#define CONFIG_SYS_FLASH_SIZE 0x800000 148#define CONFIG_SYS_MAX_FLASH_BANKS 1 149#define CONFIG_SYS_MAX_FLASH_SECT 135 150 151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 152#define CONFIG_SYS_TEXT_BASE 0x00000000 153 154#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 155#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 156#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 157 158#define CONFIG_ENV_IS_IN_FLASH 159#define CONFIG_ENV_SIZE 65536 160#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 161 162#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 163 164#define CONFIG_SYS_MALLOC_LEN (256*1024) 165#define CONFIG_SYS_DMA_ALLOC_LEN (16384) 166 167/* Allow 4MB for the kernel run-time image */ 168#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 169#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 170 171/* Other configuration settings that shouldn't have to change all that often */ 172#define CONFIG_SYS_PROMPT "U-Boot> " 173#define CONFIG_SYS_CBSIZE 256 174#define CONFIG_SYS_MAXARGS 16 175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 176#define CONFIG_SYS_LONGHELP 177 178#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 179#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) 180 181#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 182 183#endif /* __CONFIG_H */ 184