1/* 2 * U-boot - Configuration file for BF537 STAMP board 3 */ 4 5#ifndef __CONFIG_BF537_STAMP_H__ 6#define __CONFIG_BF537_STAMP_H__ 7 8#include <asm/config-pre.h> 9 10 11/* 12 * Processor Settings 13 */ 14#define CONFIG_BFIN_CPU bf537-0.2 15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 16 17 18/* 19 * Clock Settings 20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 22 */ 23/* CONFIG_CLKIN_HZ is any value in Hz */ 24#define CONFIG_CLKIN_HZ 25000000 25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 26/* 1 = CLKIN / 2 */ 27#define CONFIG_CLKIN_HALF 0 28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 29/* 1 = bypass PLL */ 30#define CONFIG_PLL_BYPASS 0 31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 32/* Values can range from 0-63 (where 0 means 64) */ 33#define CONFIG_VCO_MULT 20 34/* CCLK_DIV controls the core clock divider */ 35/* Values can be 1, 2, 4, or 8 ONLY */ 36#define CONFIG_CCLK_DIV 1 37/* SCLK_DIV controls the system clock divider */ 38/* Values can range from 1-15 */ 39#define CONFIG_SCLK_DIV 4 40 41 42/* 43 * Memory Settings 44 */ 45#define CONFIG_MEM_ADD_WDTH 10 46#define CONFIG_MEM_SIZE 64 47 48#define CONFIG_EBIU_SDRRC_VAL 0x306 49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d 50 51#define CONFIG_EBIU_AMGCTL_VAL 0xFF 52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 54 55#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 56#define CONFIG_SYS_MALLOC_LEN (384 * 1024) 57 58 59/* 60 * Network Settings 61 */ 62#ifndef __ADSPBF534__ 63#define ADI_CMDS_NETWORK 1 64#define CONFIG_BFIN_MAC 65#define CONFIG_NETCONSOLE 1 66#define CONFIG_NET_MULTI 1 67#endif 68#define CONFIG_HOSTNAME bf537-stamp 69/* Uncomment next line to use fixed MAC address */ 70/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ 71 72 73/* 74 * Flash Settings 75 */ 76#define CONFIG_FLASH_CFI_DRIVER 77#define CONFIG_SYS_FLASH_BASE 0x20000000 78#define CONFIG_SYS_FLASH_CFI 79#define CONFIG_SYS_FLASH_PROTECTION 80#define CONFIG_SYS_MAX_FLASH_BANKS 1 81/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ 82#define CONFIG_SYS_MAX_FLASH_SECT 71 83 84 85/* 86 * SPI Settings 87 */ 88#define CONFIG_BFIN_SPI 89#define CONFIG_ENV_SPI_MAX_HZ 30000000 90#define CONFIG_SF_DEFAULT_SPEED 30000000 91#define CONFIG_SPI_FLASH 92#define CONFIG_SPI_FLASH_ALL 93 94 95/* 96 * Env Storage Settings 97 */ 98#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 99#define CONFIG_ENV_IS_IN_SPI_FLASH 100#define CONFIG_ENV_OFFSET 0x10000 101#define CONFIG_ENV_SIZE 0x2000 102#define CONFIG_ENV_SECT_SIZE 0x10000 103#else 104#define CONFIG_ENV_IS_IN_FLASH 105#define CONFIG_ENV_OFFSET 0x4000 106#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 107#define CONFIG_ENV_SIZE 0x2000 108#define CONFIG_ENV_SECT_SIZE 0x2000 109#endif 110#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 111#define ENV_IS_EMBEDDED 112#else 113#define CONFIG_ENV_IS_EMBEDDED_IN_LDR 114#endif 115#ifdef ENV_IS_EMBEDDED 116/* WARNING - the following is hand-optimized to fit within 117 * the sector before the environment sector. If it throws 118 * an error during compilation remove an object here to get 119 * it linked after the configuration sector. 120 */ 121# define LDS_BOARD_TEXT \ 122 arch/blackfin/lib/libblackfin.o (.text*); \ 123 arch/blackfin/cpu/libblackfin.o (.text*); \ 124 . = DEFINED(env_offset) ? env_offset : .; \ 125 common/env_embedded.o (.text*); 126#endif 127 128 129/* 130 * I2C Settings 131 */ 132#define CONFIG_BFIN_TWI_I2C 1 133#define CONFIG_HARD_I2C 1 134 135 136/* 137 * SPI_MMC Settings 138 */ 139#define CONFIG_MMC 140#define CONFIG_GENERIC_MMC 141#define CONFIG_MMC_SPI 142 143 144/* 145 * NAND Settings 146 */ 147/* #define CONFIG_NAND_PLAT */ 148#define CONFIG_SYS_NAND_BASE 0x20212000 149#define CONFIG_SYS_MAX_NAND_DEVICE 1 150 151#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) 152#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) 153#define BFIN_NAND_WRITE(addr, cmd) \ 154 do { \ 155 bfin_write8(addr, cmd); \ 156 SSYNC(); \ 157 } while (0) 158 159#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) 160#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) 161#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 162 163 164/* 165 * CF-CARD IDE-HDD Support 166 */ 167 168/* 169 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) 170 * Strange address mapping Blackfin A13 connects to CF_A0 171 */ 172 173/* #define CONFIG_BFIN_TRUE_IDE */ 174 175/* 176 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) 177 * This should be the preferred mode 178 */ 179 180/* #define CONFIG_BFIN_CF_IDE */ 181 182/* 183 * Add IDE Disk Drive (HDD) support 184 * See example interface here: 185 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin 186 */ 187 188/* #define CONFIG_BFIN_HDD_IDE */ 189 190#if defined(CONFIG_BFIN_CF_IDE) || \ 191 defined(CONFIG_BFIN_HDD_IDE) || \ 192 defined(CONFIG_BFIN_TRUE_IDE) 193# define CONFIG_BFIN_IDE 1 194# define CONFIG_CMD_IDE 195#endif 196 197#if defined(CONFIG_BFIN_IDE) 198 199#define CONFIG_DOS_PARTITION 1 200/* 201 * IDE/ATA stuff 202 */ 203#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 204#undef CONFIG_IDE_LED /* no led for ide supported */ 205#undef CONFIG_IDE_RESET /* no reset for ide supported */ 206 207#define CONFIG_SYS_IDE_MAXBUS 1 208#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) 209 210#undef CONFIG_EBIU_AMBCTL1_VAL 211#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3 212 213#define CONFIG_CF_ATASEL_DIS 0x20311800 214#define CONFIG_CF_ATASEL_ENA 0x20311802 215 216#if defined(CONFIG_BFIN_TRUE_IDE) 217/* 218 * Note that these settings aren't for the most part used in include/ata.h 219 * when all of the ATA registers are setup 220 */ 221#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000 222#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 223#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ 224#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ 225#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ 226#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ 227 228#elif defined(CONFIG_BFIN_CF_IDE) 229#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 230#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 231#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ 232#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ 233#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ 234#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ 235 236#elif defined(CONFIG_BFIN_HDD_IDE) 237#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 238#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 239#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ 240#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ 241#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ 242#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ 243#undef CONFIG_SCLK_DIV 244#define CONFIG_SCLK_DIV 8 245#endif 246 247#endif 248 249 250/* 251 * Misc Settings 252 */ 253#define CONFIG_MISC_INIT_R 254#define CONFIG_RTC_BFIN 255#define CONFIG_UART_CONSOLE 0 256 257/* Define if want to do post memory test */ 258#undef CONFIG_POST 259#ifdef CONFIG_POST 260#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ 261#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ 262#endif 263#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC 264 265/* These are for board tests */ 266#if 0 267#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" 268#define CONFIG_AUTOBOOT_KEYED 269#define CONFIG_AUTOBOOT_PROMPT \ 270 "autoboot in %d seconds: press space to stop\n", bootdelay 271#define CONFIG_AUTOBOOT_STOP_STR " " 272#endif 273 274 275/* 276 * Pull in common ADI header for remaining command/environment setup 277 */ 278#include <configs/bfin_adi_common.h> 279 280#endif 281