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25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#include "../board/freescale/common/ics307_clk.h"
30
31#ifdef CONFIG_RAMBOOT_PBL
32#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34#endif
35
36
37#define CONFIG_BOOKE
38#define CONFIG_E500
39#define CONFIG_E500MC
40#define CONFIG_SYS_BOOK3E_HV
41#define CONFIG_MPC85xx
42#define CONFIG_FSL_CORENET
43#define CONFIG_MP
44
45#ifndef CONFIG_SYS_TEXT_BASE
46#define CONFIG_SYS_TEXT_BASE 0xeff80000
47#endif
48
49#ifndef CONFIG_RESET_VECTOR_ADDRESS
50#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51#endif
52
53#define CONFIG_SYS_FSL_CPC
54#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55#define CONFIG_FSL_ELBC
56#define CONFIG_PCI
57#define CONFIG_PCIE1
58#define CONFIG_PCIE2
59#define CONFIG_PCIE3
60#define CONFIG_FSL_PCI_INIT
61#define CONFIG_SYS_PCI_64BIT
62
63#define CONFIG_SYS_SRIO
64#define CONFIG_SRIO1
65#define CONFIG_SRIO2
66
67#define CONFIG_FSL_LAW
68
69#define CONFIG_ENV_OVERWRITE
70
71#ifdef CONFIG_SYS_NO_FLASH
72#define CONFIG_ENV_IS_NOWHERE
73#else
74#define CONFIG_FLASH_CFI_DRIVER
75#define CONFIG_SYS_FLASH_CFI
76#endif
77
78#if defined(CONFIG_SPIFLASH)
79#define CONFIG_SYS_EXTRA_ENV_RELOC
80#define CONFIG_ENV_IS_IN_SPI_FLASH
81#define CONFIG_ENV_SPI_BUS 0
82#define CONFIG_ENV_SPI_CS 0
83#define CONFIG_ENV_SPI_MAX_HZ 10000000
84#define CONFIG_ENV_SPI_MODE 0
85#define CONFIG_ENV_SIZE 0x2000
86#define CONFIG_ENV_OFFSET 0x100000
87#define CONFIG_ENV_SECT_SIZE 0x10000
88#elif defined(CONFIG_SDCARD)
89#define CONFIG_SYS_EXTRA_ENV_RELOC
90#define CONFIG_ENV_IS_IN_MMC
91#define CONFIG_SYS_MMC_ENV_DEV 0
92#define CONFIG_ENV_SIZE 0x2000
93#define CONFIG_ENV_OFFSET (512 * 1097)
94#else
95#define CONFIG_ENV_IS_IN_FLASH
96#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
97#define CONFIG_ENV_SIZE 0x2000
98#define CONFIG_ENV_SECT_SIZE 0x20000
99#endif
100
101#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
102
103
104
105
106#define CONFIG_SYS_CACHE_STASHING
107#define CONFIG_BACKSIDE_L2_CACHE
108#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
109#define CONFIG_BTB
110#define CONFIG_DDR_ECC
111#ifdef CONFIG_DDR_ECC
112#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
114#endif
115
116#define CONFIG_ENABLE_36BIT_PHYS
117
118#ifdef CONFIG_PHYS_64BIT
119#define CONFIG_ADDR_MAP
120#define CONFIG_SYS_NUM_ADDR_MAP 64
121#endif
122
123#define CONFIG_POST CONFIG_SYS_POST_MEMORY
124#define CONFIG_SYS_MEMTEST_START 0x00200000
125#define CONFIG_SYS_MEMTEST_END 0x00400000
126#define CONFIG_SYS_ALT_MEMTEST
127#define CONFIG_PANIC_HANG
128
129
130
131
132#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
133#ifdef CONFIG_PHYS_64BIT
134#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
135#else
136#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
137#endif
138#define CONFIG_SYS_L3_SIZE (1024 << 10)
139#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
140
141
142
143
144
145#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
146#define CONFIG_SYS_CCSRBAR 0xfe000000
147#ifdef CONFIG_PHYS_64BIT
148#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull
149#else
150#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
151#endif
152#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
153
154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_DCSRBAR 0xf0000000
156#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
157#endif
158
159
160#define CONFIG_ID_EEPROM
161#define CONFIG_SYS_I2C_EEPROM_NXID
162#define CONFIG_SYS_EEPROM_BUS_NUM 0
163#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
164#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
165
166
167
168
169#define CONFIG_VERY_BIG_RAM
170#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
172
173#define CONFIG_DIMM_SLOTS_PER_CTLR 1
174#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
175
176#define CONFIG_DDR_SPD
177#define CONFIG_FSL_DDR3
178
179#define CONFIG_SYS_SPD_BUS_NUM 1
180#define SPD_EEPROM_ADDRESS1 0x51
181#define SPD_EEPROM_ADDRESS2 0x52
182#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
183#define CONFIG_SYS_SDRAM_SIZE 4096
184
185
186
187
188
189
190#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
191
192#define CONFIG_SYS_FLASH_BASE 0xe0000000
193#ifdef CONFIG_PHYS_64BIT
194#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
195#else
196#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
197#endif
198
199#define CONFIG_SYS_BR0_PRELIM \
200 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
201 BR_PS_16 | BR_V)
202#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
203 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
204
205#define CONFIG_SYS_BR1_PRELIM \
206 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
207#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
208
209#define CONFIG_FSL_NGPIXIS
210#define PIXIS_BASE 0xffdf0000
211#ifdef CONFIG_PHYS_64BIT
212#define PIXIS_BASE_PHYS 0xfffdf0000ull
213#else
214#define PIXIS_BASE_PHYS PIXIS_BASE
215#endif
216
217#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
218#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
219
220#define PIXIS_LBMAP_SWITCH 7
221#define PIXIS_LBMAP_MASK 0xf0
222#define PIXIS_LBMAP_SHIFT 4
223#define PIXIS_LBMAP_ALTBANK 0x40
224
225#define CONFIG_SYS_FLASH_QUIET_TEST
226#define CONFIG_FLASH_SHOW_PROGRESS 45
227
228#define CONFIG_SYS_MAX_FLASH_BANKS 2
229#define CONFIG_SYS_MAX_FLASH_SECT 1024
230#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500
232
233#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
234
235#if defined(CONFIG_RAMBOOT_PBL)
236#define CONFIG_SYS_RAMBOOT
237#endif
238
239
240#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
241#define CONFIG_NAND_FSL_ELBC
242#ifdef CONFIG_NAND_FSL_ELBC
243#define CONFIG_SYS_NAND_BASE 0xffa00000
244#ifdef CONFIG_PHYS_64BIT
245#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
246#else
247#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
248#endif
249
250#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
251#define CONFIG_SYS_MAX_NAND_DEVICE 1
252#define CONFIG_MTD_NAND_VERIFY_WRITE
253#define CONFIG_CMD_NAND
254#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
255
256
257#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
258 | (2<<BR_DECC_SHIFT) \
259 | BR_PS_8 \
260 | BR_MS_FCM \
261 | BR_V)
262#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
263 | OR_FCM_PGS \
264 | OR_FCM_CSCT \
265 | OR_FCM_CST \
266 | OR_FCM_CHT \
267 | OR_FCM_SCY_1 \
268 | OR_FCM_TRLX \
269 | OR_FCM_EHTR)
270
271#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
272#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
273#endif
274#endif
275
276#define CONFIG_SYS_FLASH_EMPTY_INFO
277#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
278#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
279
280#define CONFIG_BOARD_EARLY_INIT_F
281#define CONFIG_BOARD_EARLY_INIT_R
282#define CONFIG_MISC_INIT_R
283
284#define CONFIG_HWCONFIG
285
286
287#define CONFIG_L1_INIT_RAM
288#define CONFIG_SYS_INIT_RAM_LOCK
289#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
290#ifdef CONFIG_PHYS_64BIT
291#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
292#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
293
294#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
295 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
296 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
297#else
298#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
299#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
300#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
301#endif
302#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
303
304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
305#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
306
307#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
308#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
309
310
311
312
313
314#define CONFIG_CONS_INDEX 1
315#define CONFIG_SYS_NS16550
316#define CONFIG_SYS_NS16550_SERIAL
317#define CONFIG_SYS_NS16550_REG_SIZE 1
318#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
319
320#define CONFIG_SYS_BAUDRATE_TABLE \
321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
322
323#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
324#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
325#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
326#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
327
328
329#define CONFIG_SYS_HUSH_PARSER
330#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
331
332
333#define CONFIG_OF_LIBFDT
334#define CONFIG_OF_BOARD_SETUP
335#define CONFIG_OF_STDOUT_VIA_ALIAS
336
337
338#define CONFIG_FIT
339#define CONFIG_FIT_VERBOSE
340
341
342#define CONFIG_FSL_I2C
343#define CONFIG_HARD_I2C
344#define CONFIG_I2C_MULTI_BUS
345#define CONFIG_I2C_CMD_TREE
346#define CONFIG_SYS_I2C_SPEED 400000
347#define CONFIG_SYS_I2C_SLAVE 0x7F
348#define CONFIG_SYS_I2C_OFFSET 0x118000
349#define CONFIG_SYS_I2C2_OFFSET 0x118100
350
351
352
353
354#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
355#ifdef CONFIG_PHYS_64BIT
356#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
357#else
358#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
359#endif
360#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
361
362#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
363#ifdef CONFIG_PHYS_64BIT
364#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
365#else
366#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
367#endif
368#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
369
370
371
372
373#define CONFIG_FSL_ESPI
374#define CONFIG_SPI_FLASH
375#define CONFIG_SPI_FLASH_SPANSION
376#define CONFIG_CMD_SF
377#define CONFIG_SF_DEFAULT_SPEED 10000000
378#define CONFIG_SF_DEFAULT_MODE 0
379
380
381
382
383
384
385
386#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
387#ifdef CONFIG_PHYS_64BIT
388#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
389#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
390#else
391#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
392#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
393#endif
394#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
395#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
396#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
397#ifdef CONFIG_PHYS_64BIT
398#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
399#else
400#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
401#endif
402#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
403
404
405#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
406#ifdef CONFIG_PHYS_64BIT
407#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
408#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
409#else
410#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
411#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
412#endif
413#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
414#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
415#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
416#ifdef CONFIG_PHYS_64BIT
417#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
418#else
419#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
420#endif
421#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
422
423
424#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
425#ifdef CONFIG_PHYS_64BIT
426#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
427#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
428#else
429#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
430#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
431#endif
432#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
433#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
434#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
435#ifdef CONFIG_PHYS_64BIT
436#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
437#else
438#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
439#endif
440#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
441
442
443#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
444#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
445#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000
446#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
447#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
448#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
449
450
451#define CONFIG_SYS_DPAA_QBMAN
452#define CONFIG_SYS_BMAN_NUM_PORTALS 10
453#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
454#ifdef CONFIG_PHYS_64BIT
455#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
456#else
457#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
458#endif
459#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
460#define CONFIG_SYS_QMAN_NUM_PORTALS 10
461#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
462#ifdef CONFIG_PHYS_64BIT
463#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
464#else
465#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
466#endif
467#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
468
469#define CONFIG_SYS_DPAA_FMAN
470#define CONFIG_SYS_DPAA_PME
471
472#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
473#ifdef CONFIG_PHYS_64BIT
474#define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL
475#else
476#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
477#endif
478
479#ifdef CONFIG_SYS_DPAA_FMAN
480#define CONFIG_FMAN_ENET
481#endif
482
483#ifdef CONFIG_PCI
484#define CONFIG_NET_MULTI
485#define CONFIG_PCI_PNP
486#define CONFIG_E1000
487
488#define CONFIG_PCI_SCAN_SHOW
489#define CONFIG_DOS_PARTITION
490#endif
491
492
493#ifdef CONFIG_FSL_SATA_V2
494#define CONFIG_LIBATA
495#define CONFIG_FSL_SATA
496
497#define CONFIG_SYS_SATA_MAX_DEVICE 2
498#define CONFIG_SATA1
499#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
500#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
501#define CONFIG_SATA2
502#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
503#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
504
505#define CONFIG_LBA48
506#define CONFIG_CMD_SATA
507#define CONFIG_DOS_PARTITION
508#define CONFIG_CMD_EXT2
509#endif
510
511#ifdef CONFIG_FMAN_ENET
512#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
513#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
514#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
515#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
516#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
517
518#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
519#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
520#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
521#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
522#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
523
524#define CONFIG_SYS_TBIPA_VALUE 8
525#define CONFIG_MII
526#define CONFIG_ETHPRIME "FM1@DTSEC1"
527#define CONFIG_PHY_GIGE
528#endif
529
530
531
532
533#define CONFIG_LOADS_ECHO
534#define CONFIG_SYS_LOADS_BAUD_CHANGE
535
536
537
538
539#include <config_cmd_default.h>
540
541#define CONFIG_CMD_DHCP
542#define CONFIG_CMD_ELF
543#define CONFIG_CMD_ERRATA
544#define CONFIG_CMD_GREPENV
545#define CONFIG_CMD_IRQ
546#define CONFIG_CMD_I2C
547#define CONFIG_CMD_MII
548#define CONFIG_CMD_PING
549#define CONFIG_CMD_SETEXPR
550
551#ifdef CONFIG_PCI
552#define CONFIG_CMD_PCI
553#define CONFIG_CMD_NET
554#endif
555
556
557
558
559#define CONFIG_CMD_USB
560#define CONFIG_USB_STORAGE
561#define CONFIG_USB_EHCI
562#define CONFIG_USB_EHCI_FSL
563#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
564#define CONFIG_CMD_EXT2
565
566#define CONFIG_MMC
567
568#ifdef CONFIG_MMC
569#define CONFIG_FSL_ESDHC
570#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
571#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
572#define CONFIG_CMD_MMC
573#define CONFIG_GENERIC_MMC
574#define CONFIG_CMD_EXT2
575#define CONFIG_CMD_FAT
576#define CONFIG_DOS_PARTITION
577#endif
578
579
580
581
582#define CONFIG_SYS_LONGHELP
583#define CONFIG_CMDLINE_EDITING
584#define CONFIG_AUTO_COMPLETE
585#define CONFIG_SYS_LOAD_ADDR 0x2000000
586#define CONFIG_SYS_PROMPT "=> "
587#ifdef CONFIG_CMD_KGDB
588#define CONFIG_SYS_CBSIZE 1024
589#else
590#define CONFIG_SYS_CBSIZE 256
591#endif
592#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
593#define CONFIG_SYS_MAXARGS 16
594#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
595#define CONFIG_SYS_HZ 1000
596
597
598
599
600
601
602#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
603#define CONFIG_SYS_BOOTM_LEN (64 << 20)
604
605#ifdef CONFIG_CMD_KGDB
606#define CONFIG_KGDB_BAUDRATE 230400
607#define CONFIG_KGDB_SER_INDEX 2
608#endif
609
610
611
612
613#define CONFIG_ROOTPATH /opt/nfsroot
614#define CONFIG_BOOTFILE uImage
615#define CONFIG_UBOOTPATH u-boot.bin
616
617
618#define CONFIG_LOADADDR 1000000
619
620#define CONFIG_BOOTDELAY 10
621
622#define CONFIG_BAUDRATE 115200
623
624#define CONFIG_EXTRA_ENV_SETTINGS \
625 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
626 "bank_intlv=cs0_cs1\0" \
627 "netdev=eth0\0" \
628 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
629 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot && " \
631 "protect off $ubootaddr +$filesize && " \
632 "erase $ubootaddr +$filesize && " \
633 "cp.b $loadaddr $ubootaddr $filesize && " \
634 "protect on $ubootaddr +$filesize && " \
635 "cmp.b $loadaddr $ubootaddr $filesize\0" \
636 "consoledev=ttyS0\0" \
637 "ramdiskaddr=2000000\0" \
638 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
639 "fdtaddr=c00000\0" \
640 "fdtfile=p4080ds/p4080ds.dtb\0" \
641 "bdev=sda3\0" \
642 "c=ffe\0" \
643 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
644
645#define CONFIG_HDBOOT \
646 "setenv bootargs root=/dev/$bdev rw " \
647 "console=$consoledev,$baudrate $othbootargs;" \
648 "tftp $loadaddr $bootfile;" \
649 "tftp $fdtaddr $fdtfile;" \
650 "bootm $loadaddr - $fdtaddr"
651
652#define CONFIG_NFSBOOTCOMMAND \
653 "setenv bootargs root=/dev/nfs rw " \
654 "nfsroot=$serverip:$rootpath " \
655 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
656 "console=$consoledev,$baudrate $othbootargs;" \
657 "tftp $loadaddr $bootfile;" \
658 "tftp $fdtaddr $fdtfile;" \
659 "bootm $loadaddr - $fdtaddr"
660
661#define CONFIG_RAMBOOTCOMMAND \
662 "setenv bootargs root=/dev/ram rw " \
663 "console=$consoledev,$baudrate $othbootargs;" \
664 "tftp $ramdiskaddr $ramdiskfile;" \
665 "tftp $loadaddr $bootfile;" \
666 "tftp $fdtaddr $fdtfile;" \
667 "bootm $loadaddr $ramdiskaddr $fdtaddr"
668
669#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
670
671#endif
672