1/* 2 * Copyright 2011 Alex Dubov <oakad@yahoo.com> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23/* 24 * Merury Computers MPQ101 board configuration file 25 * 26 */ 27#ifndef __CONFIG_H 28#define __CONFIG_H 29 30#ifdef CONFIG_36BIT 31# define CONFIG_PHYS_64BIT 32#endif 33 34/* High Level Configuration Options */ 35#define CONFIG_BOOKE /* BOOKE */ 36#define CONFIG_E500 /* BOOKE e500 family */ 37#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 38#define CONFIG_MPC8548 /* MPC8548 specific */ 39#define CONFIG_MPQ101 /* MPQ101 board specific */ 40 41#define CONFIG_SYS_SRIO /* enable serial RapidIO */ 42#define CONFIG_TSEC_ENET /* tsec ethernet support */ 43#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 44#define CONFIG_FSL_LAW /* Use common FSL init code */ 45 46/* 47 * These can be toggled for performance analysis, otherwise use default. 48 */ 49#define CONFIG_L2_CACHE /* toggle L2 cache */ 50#define CONFIG_BTB /* toggle branch predition */ 51 52#define CONFIG_PANIC_HANG 53 54/* 55 * Only possible on E500 Version 2 or newer cores. 56 */ 57#define CONFIG_ENABLE_36BIT_PHYS 58 59#ifdef CONFIG_PHYS_64BIT 60# define CONFIG_ADDR_MAP 61# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 62#endif 63 64 65#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ 66 67/* 68 * Base addresses -- Note these are effective addresses where the 69 * actual resources get mapped (not physical addresses) 70 */ 71#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 72#define CONFIG_SYS_CCSRBAR 0xe0000000 73 74#ifdef CONFIG_PHYS_64BIT 75# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull 76#else 77# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 78#endif 79 80#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 81 82/* DDR Setup */ 83#define CONFIG_FSL_DDR2 84 85#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 86 87#define CONFIG_MEM_INIT_VALUE 0xDeadBeef 88#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 90 91#define CONFIG_NUM_DDR_CONTROLLERS 1 92#define CONFIG_DIMM_SLOTS_PER_CTLR 1 93#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 94 95/* Fixed 512MB DDR2 parameters */ 96#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */ 97#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 98#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 99#define CONFIG_SYS_DDR_TIMING_3 0x00010000 100#define CONFIG_SYS_DDR_TIMING_0 0x00260802 101#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432 102#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322 103#define CONFIG_SYS_DDR_TIMING_2 0x03984cce 104#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca 105#define CONFIG_SYS_DDR_MODE_1 0x00400442 106#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432 107#define CONFIG_SYS_DDR_MODE_2 0x00000000 108#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000 109#define CONFIG_SYS_DDR_INTERVAL 0x08200100 110#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100 111#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 112#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */ 113#define CONFIG_SYS_DDR_CONTROL2 0x04400000 114 115#define CONFIG_SYS_ALT_MEMTEST 116#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ 117#define CONFIG_SYS_MEMTEST_END 0x0ffffffc 118 119/* 120 * RAM definitions 121 */ 122#define CONFIG_SYS_INIT_RAM_LOCK 123#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 124#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 125 126#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 127 - GENERATED_GBL_DATA_SIZE) 128#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 129 130#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 131#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 132 133/* 134 * Local Bus Definitions 135 */ 136#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 137#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 138 139 140/* 141 * FLASH on the Local Bus 142 * One bank, 128M, using the CFI driver. 143 */ 144#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ 145#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ 146 147#ifdef CONFIG_PHYS_64BIT 148# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull 149#else 150# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 151#endif 152 153/* 0xf8001801 */ 154#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 155 | BR_PS_32 | BR_V) 156 157/* 0xf8006ff7 */ 158#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \ 159 | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ 160 | OR_GPCM_SCY_15 | OR_GPCM_TRLX \ 161 | OR_GPCM_EHTR | OR_GPCM_EAD) 162 163#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 164#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 165 166#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 167#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 168 169#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 170#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 171 172#define CONFIG_FLASH_CFI_DRIVER 173#define CONFIG_SYS_FLASH_CFI 174#define CONFIG_SYS_FLASH_EMPTY_INFO 175#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 176/* 177 * When initializing flash, if we cannot find the manufacturer ID, 178 * assume this is the AMD flash. 179 */ 180#define CONFIG_ASSUME_AMD_FLASH 181 182/* 183 * Environment parameters 184 */ 185#define CONFIG_ENV_IS_IN_FLASH 186#define CONFIG_ENV_OVERWRITE 187#define CONFIG_SYS_USE_PPCENV 188#define ENV_IS_EMBEDDED 189#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ 190#define CONFIG_ENV_SIZE 0x800 191 192/* Environment at the start of flash sector, before text. */ 193#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE) 194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 195#define CONFIG_SYS_TEXT_BASE 0xfffc0800 196#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds" 197 198/* 199 * Cypress CY7C67200 USB controller on the Local Bus. 200 * Not supported by u-boot at present. 201 */ 202#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 203 204#ifdef CONFIG_PHYS_64BIT 205# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull 206#else 207# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE 208#endif 209 210/* 0xf0001001 */ 211#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ 212 | BR_PS_16 | BR_V) 213 214/* fffff002 */ 215#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ 216 | OR_GPCM_BCTLD | OR_GPCM_EHTR) 217 218/* 219 * Serial Ports 220 */ 221#define CONFIG_CONS_INDEX 2 222#define CONFIG_SYS_NS16550 223#define CONFIG_SYS_NS16550_SERIAL 224#define CONFIG_SYS_NS16550_REG_SIZE 1 225#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 226 227#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ 228 19200, 38400, 115200} 229 230#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 231#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 232 233/* 234 * I2C buses and peripherals 235 */ 236#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 237#define CONFIG_HARD_I2C /* I2C with hardware support*/ 238#define CONFIG_I2C_MULTI_BUS 239#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 240#define CONFIG_SYS_I2C_SLAVE 0x7f 241#define CONFIG_SYS_I2C_OFFSET 0x3000 242#define CONFIG_SYS_I2C2_OFFSET 0x3100 243 244/* I2C RTC - M41T81 */ 245#define CONFIG_RTC_M41T62 246#define CONFIG_SYS_I2C_RTC_ADDR 0x68 247#define CONFIG_SYS_M41T11_BASE_YEAR 2000 248 249/* I2C EEPROM - 24C256 */ 250#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 251#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 252#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 253#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 254#define CONFIG_SYS_EEPROM_BUS_NUM 1 255 256/* 257 * RapidIO MMU 258 */ 259#ifdef CONFIG_SYS_SRIO 260# define CONFIG_SRIO1 261# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 262# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 263 264# ifdef CONFIG_PHYS_64BIT 265# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull 266# else 267# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT 268# endif 269#endif 270 271/* 272 * Ethernet 273 */ 274#ifdef CONFIG_TSEC_ENET 275 276# ifndef CONFIG_NET_MULTI 277# define CONFIG_NET_MULTI 278# endif 279 280# define CONFIG_MII /* MII PHY management */ 281# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 282 283# define CONFIG_TSEC1 284# define CONFIG_TSEC1_NAME "eTSEC0" 285# define TSEC1_PHY_ADDR 0x10 286# define TSEC1_PHYIDX 0 287# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 288 289# define CONFIG_TSEC2 290# define CONFIG_TSEC2_NAME "eTSEC1" 291# define TSEC2_PHY_ADDR 0x11 292# define TSEC2_PHYIDX 0 293# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 294 295# define CONFIG_TSEC3 296# define CONFIG_TSEC3_NAME "eTSEC2" 297# define TSEC3_PHY_ADDR 0x12 298# define TSEC3_PHYIDX 0 299# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 301# define CONFIG_TSEC4 302# define CONFIG_TSEC4_NAME "eTSEC3" 303# define TSEC4_PHY_ADDR 0x13 304# define TSEC4_PHYIDX 0 305# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 306 307/* Options are: eTSEC[0-3] */ 308# define CONFIG_ETHPRIME "eTSEC0" 309# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 310#endif 311 312/* 313 * Command line configuration. 314 */ 315#include <config_cmd_default.h> 316 317#define CONFIG_CMD_DATE 318#define CONFIG_CMD_DHCP 319#define CONFIG_CMD_PING 320#define CONFIG_CMD_SNTP 321#define CONFIG_CMD_I2C 322#define CONFIG_CMD_EEPROM 323#define CONFIG_CMD_MII 324#define CONFIG_CMD_ELF 325#define CONFIG_CMD_IRQ 326#define CONFIG_CMD_SETEXPR 327#define CONFIG_CMD_JFFS2 328 329/* 330 * Miscellaneous configurable options 331 */ 332 333/* pass open firmware flat tree */ 334#define CONFIG_OF_LIBFDT 335#define CONFIG_OF_BOARD_SETUP 336#define CONFIG_OF_STDOUT_VIA_ALIAS 337 338#define CONFIG_FIT /* new uImage format support */ 339#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 340 341/* Use the HUSH parser */ 342#define CONFIG_SYS_HUSH_PARSER 343 344#ifdef CONFIG_SYS_HUSH_PARSER 345# define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 346#endif 347 348#define CONFIG_LOADS_ECHO /* echo on for serial download */ 349#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 350 351#define CONFIG_SYS_LONGHELP /* undef to save memory */ 352#define CONFIG_CMDLINE_EDITING /* Command-line editing */ 353#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 354 355#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 356#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */ 357 358/* Console I/O Buffer Size */ 359#ifdef CONFIG_CMD_KGDB 360# define CONFIG_SYS_CBSIZE 1024 361#else 362# define CONFIG_SYS_CBSIZE 256 363#endif 364 365/* Print Buffer Size */ 366#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 367 368#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 369#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 370#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 371 372/* 373 * For booting Linux, the board info and command line data 374 * have to be in the first 16 MB of memory, since this is 375 * the maximum mapped by the Linux kernel during initialization. 376 */ 377#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 378#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 379 380#ifdef CONFIG_CMD_KGDB 381# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 382# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 383#endif 384 385/* 386 * Basic Environment Configuration 387 */ 388#define CONFIG_BAUDRATE 115200 389#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 390 391/*default location for tftp and bootm*/ 392#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 393 394#endif /* __CONFIG_H */ 395