1/* 2 * (C) Copyright 2004 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Kshitij Gupta <kshitij@ti.com> 6 * 7 * Configuration settings for the 242x TI H4 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 */ 34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 35#define CONFIG_OMAP 1 /* in a TI OMAP core */ 36#define CONFIG_OMAP2420 1 /* which is in a 2420 */ 37#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ 38/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ 39/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ 40 41#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 42 43/* Clock config to target*/ 44#define PRCM_CONFIG_II 1 45/* #define PRCM_CONFIG_III 1 */ 46 47#include <asm/arch/omap2420.h> /* get chip and board defs */ 48 49/* On H4, NOR and NAND flash are mutual exclusive. 50 Define this if you want to use NAND 51 */ 52/*#define CONFIG_SYS_NAND_BOOT */ 53 54#ifdef CONFIG_APTIX 55#define V_SCLK 1500000 56#else 57#define V_SCLK 12000000 58#endif 59 60/* input clock of PLL */ 61/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ 62#define CONFIG_SYS_CLK_FREQ V_SCLK 63 64#undef CONFIG_USE_IRQ /* no support for IRQs */ 65#define CONFIG_MISC_INIT_R 66 67#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 68#define CONFIG_SETUP_MEMORY_TAGS 1 69#define CONFIG_INITRD_TAG 1 70#define CONFIG_REVISION_TAG 1 71 72/* 73 * Size of malloc() pool 74 */ 75#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ 76#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 77 78/* 79 * Hardware drivers 80 */ 81 82/* 83 * SMC91c96 Etherent 84 */ 85#define CONFIG_NET_MULTI 86#define CONFIG_LAN91C96 87#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) 88#define CONFIG_LAN91C96_EXT_PHY 89 90/* 91 * NS16550 Configuration 92 */ 93#ifdef CONFIG_APTIX 94#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ 95#else 96#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ 97#endif 98 99#define CONFIG_SYS_NS16550 100#define CONFIG_SYS_NS16550_SERIAL 101#define CONFIG_SYS_NS16550_REG_SIZE (-4) 102#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ 103#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 104 105/* 106 * select serial console configuration 107 */ 108#define CONFIG_SERIAL1 1 /* UART1 on H4 */ 109 110 /* 111 * I2C configuration 112 */ 113#define CONFIG_HARD_I2C 114#define CONFIG_SYS_I2C_SPEED 100000 115#define CONFIG_SYS_I2C_SLAVE 1 116#define CONFIG_DRIVER_OMAP24XX_I2C 117 118/* allow to overwrite serial and ethaddr */ 119#define CONFIG_ENV_OVERWRITE 120#define CONFIG_CONS_INDEX 1 121#define CONFIG_BAUDRATE 115200 122#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 123 124 125/* 126 * Command line configuration. 127 */ 128#include <config_cmd_default.h> 129 130#ifdef CONFIG_SYS_NAND_BOOT 131 #define CONFIG_CMD_DHCP 132 #define CONFIG_CMD_I2C 133 #define CONFIG_CMD_NAND 134 #define CONFIG_CMD_JFFS2 135#else 136 #define CONFIG_CMD_DHCP 137 #define CONFIG_CMD_I2C 138 #define CONFIG_CMD_JFFS2 139 140 #undef CONFIG_CMD_SOURCE 141#endif 142 143 144/* 145 * BOOTP options 146 */ 147#define CONFIG_BOOTP_SUBNETMASK 148#define CONFIG_BOOTP_GATEWAY 149#define CONFIG_BOOTP_HOSTNAME 150#define CONFIG_BOOTP_BOOTPATH 151 152#define CONFIG_BOOTDELAY 3 153 154#ifdef NFS_BOOT_DEFAULTS 155#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" 156#else 157#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" 158#endif 159 160#define CONFIG_NETMASK 255.255.254.0 161#define CONFIG_IPADDR 128.247.77.90 162#define CONFIG_SERVERIP 128.247.77.158 163#define CONFIG_BOOTFILE "uImage" 164 165/* 166 * Miscellaneous configurable options 167 */ 168#define CONFIG_SYS_LONGHELP /* undef to save memory */ 169#ifdef CONFIG_APTIX 170# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " 171#else 172# define CONFIG_SYS_PROMPT "OMAP242x H4 # " 173#endif 174#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 175/* Print Buffer Size */ 176#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 177#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 178#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 179 180#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ 181#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) 182 183#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ 184 185/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 186 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 187 */ 188#ifdef CONFIG_APTIX 189#define V_PTV 3 190#else 191#define V_PTV 7 /* use with 12MHz/128 */ 192#endif 193 194#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 195#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ 196#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) 197 198/*----------------------------------------------------------------------- 199 * Stack sizes 200 * 201 * The stack sizes are set up in start.S using the settings below 202 */ 203#define CONFIG_STACKSIZE SZ_128K /* regular stack */ 204#ifdef CONFIG_USE_IRQ 205#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 206#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 207#endif 208 209/*----------------------------------------------------------------------- 210 * Physical Memory Map 211 */ 212#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 213#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 214#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 215#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 216 217#define PHYS_FLASH_SECT_SIZE SZ_128K 218#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ 219#define PHYS_FLASH_SIZE_1 SZ_32M 220#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ 221#define PHYS_FLASH_SIZE_2 SZ_32M 222 223#define PHYS_SRAM 0x4020F800 224/*----------------------------------------------------------------------- 225 * FLASH and environment organization 226 */ 227#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 228#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 229#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ 230#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 231#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */ 232#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 } 233 234#ifdef CONFIG_SYS_NAND_BOOT 235#define CONFIG_ENV_IS_IN_NAND 1 236#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ 237#else 238#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) 239#define CONFIG_ENV_IS_IN_FLASH 1 240#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE 241#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ 242#endif 243 244/*----------------------------------------------------------------------- 245 * CFI FLASH driver setup 246 */ 247#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 248#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ 249#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 250#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 251 252/* timeout values are in ticks */ 253#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 254#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 255 256#define CONFIG_SYS_JFFS2_MEM_NAND 257 258/* 259 * JFFS2 partitions 260 */ 261/* No command line, one static partition, whole device */ 262#undef CONFIG_CMD_MTDPARTS 263#define CONFIG_JFFS2_DEV "nor1" 264#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 265#define CONFIG_JFFS2_PART_OFFSET 0x00000000 266 267/* mtdparts command line support */ 268/* Note: fake mtd_id used, no linux mtd map file */ 269/* 270#define CONFIG_CMD_MTDPARTS 271#define MTDIDS_DEFAULT "nor1=omap2420-1" 272#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" 273*/ 274 275#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 276#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM 277 278#endif /* __CONFIG_H */ 279