LXR uboot/include/ns87308.h

   1/*
   2 * (C) Copyright 2000
   3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef _NS87308_H_
  25#define _NS87308_H_
  26
  27#include <asm/pci_io.h>
  28
  29/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
  30   functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
  31
  32void initialise_ns87308(void);
  33
  34/*
  35 * The following struct represents the GPIO registers on the NS87308/NS97307
  36 */
  37struct GPIO
  38{
  39  unsigned char dta1;  /* 0 data port 1 */
  40  unsigned char dir1;  /* 1 direction port 1 */
  41  unsigned char out1;  /* 2 output type port 1 */
  42  unsigned char puc1;  /* 3 pull-up control port 1 */
  43  unsigned char dta2;  /* 4 data port 2 */
  44  unsigned char dir2;  /* 5 direction port 2 */
  45  unsigned char out2;  /* 6 output type port 2 */
  46  unsigned char puc2;  /* 7 pull-up control port 2  */
  47};
  48
  49/*
  50 * The following represents the power management registers on the NS87308/NS97307
  51 */
  52#define PWM_FER1 0  /* 0 function enable reg. 1 */
  53#define PWM_FER2 1  /* 1 function enable reg. 2 */
  54#define PWM_PMC1 2  /* 2 power mgmt. control 1 */
  55#define PWM_PMC2 3  /* 3 power mgmt. control 2 */
  56#define PWM_PMC3 4  /* 4 power mgmt. control 3 */
  57#define PWM_WDTO 5  /* 5 watchdog time-out */
  58#define PWM_WDCF 6  /* 6 watchdog config. */
  59#define PWM_WDST 7  /* 7 watchdog status  */
  60
  61/*PNP config registers:
  62 * these depend on the stated of BADDR1 and BADDR0 on startup
  63 * so there's three versions here with the last two digits indicating
  64 * for which configuration their valid
  65 * the 1st of the two digits indicates the state of BADDR1
  66 * the 2st of the two digits indicates the state of BADDR0
  67 */
  68
  69
  70#define IO_INDEX_OFFSET_0x 0x0279  /* full PnP isa Mode */
  71#define IO_INDEX_OFFSET_10 0x015C  /* PnP motherboard mode */
  72#define IO_INDEX_OFFSET_11 0x002E  /* PnP motherboard mode */
  73#define IO_DATA_OFFSET_0x  0x0A79  /* full PnP isa Mode */
  74#define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
  75#define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
  76
  77#if defined(CONFIG_SYS_NS87308_BADDR_0x)
  78#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
  79#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
  80#elif defined(CONFIG_SYS_NS87308_BADDR_10)
  81#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
  82#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
  83#elif defined(CONFIG_SYS_NS87308_BADDR_11)
  84#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
  85#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
  86#endif
  87
  88/* PnP register definitions */
  89
  90#define SET_RD_DATA_PORT    0x00
  91#define SERIAL_ISOLATION    0x01
  92#define CONFIG_CONTROL      0x02
  93#define WAKE_CSN            0x03
  94#define RES_DATA            0x04
  95#define STATUS              0x05
  96#define SET_CSN             0x06
  97#define LOGICAL_DEVICE      0x07
  98
  99/*vendor defined values */
 100#define SID_REG             0x20
 101#define SUPOERIO_CONF1      0x21
 102#define SUPOERIO_CONF2      0x22
 103#define PGCS_INDEX          0x23
 104#define PGCS_DATA           0x24
 105
 106/* values above 30 are different for each logical device
 107   but I can't be arsed to enter them all. the ones here
 108   are pretty consistent between all logical devices
 109   feel free to correct the situation if you want.. ;)
 110   */
 111#define ACTIVATE            0x30
 112#define ACTIVATE_OFF        0x00
 113#define ACTIVATE_ON         0x01
 114
 115#define BASE_ADDR_HIGH      0x60
 116#define BASE_ADDR_LOW       0x61
 117#define LUN_CONFIG_REG          0xF0
 118#define DBASE_HIGH                      0x60    /* SIO KBC data base address, 15:8 */
 119#define DBASE_LOW                       0x61    /* SIO KBC data base address,  7:0 */
 120#define CBASE_HIGH                      0x62    /* SIO KBC command base addr, 15:8 */
 121#define CBASE_LOW                       0x63    /* SIO KBC command base addr,  7:0 */
 122
 123/* the logical devices*/
 124#define LDEV_KBC1           0x00        /* 2 devices for keyboard and mouse controller*/
 125#define LDEV_KBC2           0x01
 126#define LDEV_MOUSE          0x01
 127#define LDEV_RTC_APC        0x02        /*Real Time Clock and Advanced Power Control*/
 128#define LDEV_FDC            0x03        /*floppy disk controller*/
 129#define LDEV_PARP           0x04        /*Parallel port*/
 130#define LDEV_UART2          0x05
 131#define LDEV_UART1          0x06
 132#define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
 133#define LDEV_POWRMAN        0x08    /*Power Managment*/
 134
 135#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
 136#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
 137#define CONFIG_SYS_NS87308_MOUSE        (1 << LDEV_MOUSE)
 138#define CONFIG_SYS_NS87308_RTC_APC      (1 << LDEV_RTC_APC)
 139#define CONFIG_SYS_NS87308_FDC          (1 << LDEV_FDC)
 140#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
 141#define CONFIG_SYS_NS87308_UART2        (1 << LDEV_UART2)
 142#define CONFIG_SYS_NS87308_UART1        (1 << LDEV_UART1)
 143#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
 144#define CONFIG_SYS_NS87308_POWRMAN      (1 << LDEV_POWRMAN)
 145
 146/*some functions and macro's for doing configuration */
 147
 148static inline void read_pnp_config(unsigned char index, unsigned char *data)
 149{
 150    pci_writeb(index,IO_INDEX);
 151    pci_readb(IO_DATA, *data);
 152}
 153
 154static inline void write_pnp_config(unsigned char index, unsigned char data)
 155{
 156    pci_writeb(index,IO_INDEX);
 157    pci_writeb(data, IO_DATA);
 158}
 159
 160static inline void pnp_set_device(unsigned char dev)
 161{
 162    write_pnp_config(LOGICAL_DEVICE, dev);
 163}
 164
 165static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
 166{
 167    pci_writeb(index, CONFIG_SYS_ISA_IO + base);
 168    eieio();
 169    pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
 170}
 171
 172/*void write_pnp_config(unsigned char index, unsigned char data);
 173void pnp_set_device(unsigned char dev);
 174*/
 175
 176#define PNP_SET_DEVICE_BASE(dev,base) \
 177   pnp_set_device(dev); \
 178   write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
 179   write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
 180   write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
 181   write_pnp_config(ACTIVATE, ACTIVATE_ON);
 182
 183#define PNP_ACTIVATE_DEVICE(dev) \
 184   pnp_set_device(dev); \
 185   write_pnp_config(ACTIVATE, ACTIVATE_ON);
 186
 187#define PNP_DEACTIVATE_DEVICE(dev) \
 188   pnp_set_device(dev); \
 189   write_pnp_config(ACTIVATE, ACTIVATE_OFF);
 190
 191
 192static inline void write_pgcs_config(unsigned char index, unsigned char data)
 193{
 194    write_pnp_config(PGCS_INDEX, index);
 195    write_pnp_config(PGCS_DATA, data);
 196}
 197
 198/* these macrose configure the 3 CS lines
 199   on the sandpoint board these controll NVRAM
 200   CS0 is connected to NVRAMCS
 201   CS1 is connected to NVRAMAS0
 202   CS2 is connected to NVRAMAS1
 203   */
 204#define PGCS_CS_ASSERT_ON_WRITE 0x10
 205#define PGCS_CS_ASSERT_ON_READ  0x20
 206
 207#define PNP_PGCS_CSLINE_BASE(cs, base) \
 208  write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
 209  write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
 210
 211#define PNP_PGCS_CSLINE_CONF(cs, conf) \
 212  write_pgcs_config(((cs) << 2) + 2, (conf) );
 213
 214
 215/* The following sections are for 87308 extensions to the standard compoents it emulates */
 216
 217/* extensions to 16550*/
 218
 219#define MCR_MDSL_MSK    0xe0 /*mode select mask*/
 220#define MCR_MDSL_UART   0x00 /*uart, default*/
 221#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
 222#define MCR_MDSL_SIR    0x03 /*SIR*/
 223#define MCR_MDSL_CIR    0x06 /*Consumer IR*/
 224
 225#define FCR_TXFTH0      0x10    /* these bits control threshod of data level in fifo */
 226#define FCR_TXFTH1      0x20    /* for interrupt trigger */
 227
 228/*
 229 * Default NS87308 configuration
 230 */
 231#ifndef CONFIG_SYS_NS87308_KBC1_BASE
 232#define CONFIG_SYS_NS87308_KBC1_BASE    0x0060
 233#endif
 234#ifndef CONFIG_SYS_NS87308_RTC_BASE
 235#define CONFIG_SYS_NS87308_RTC_BASE     0x0070
 236#endif
 237#ifndef CONFIG_SYS_NS87308_FDC_BASE
 238#define CONFIG_SYS_NS87308_FDC_BASE     0x03F0
 239#endif
 240#ifndef CONFIG_SYS_NS87308_LPT_BASE
 241#define CONFIG_SYS_NS87308_LPT_BASE     0x0278
 242#endif
 243#ifndef CONFIG_SYS_NS87308_UART1_BASE
 244#define CONFIG_SYS_NS87308_UART1_BASE   0x03F8
 245#endif
 246#ifndef CONFIG_SYS_NS87308_UART2_BASE
 247#define CONFIG_SYS_NS87308_UART2_BASE   0x02F8
 248#endif
 249
 250#endif /*_NS87308_H_*/
 251