LXR uboot/arch/arm/cpu/armv7/omap4/omap4_mux

   1 /*
   2 * (C) Copyright 2010
   3 * Texas Instruments Incorporated, <www.ti.com>
   4 *
   5 *      Balaji Krishnamoorthy   <balajitk@ti.com>
   6 *      Aneesh V                <aneesh@ti.com>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26#ifndef _OMAP4_MUX_DATA_H_
  27#define _OMAP4_MUX_DATA_H_
  28
  29#include <asm/arch/mux_omap4.h>
  30
  31const struct pad_conf_entry core_padconf_array_essential[] = {
  32
  33{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
  34{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
  35{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
  36{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
  37{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
  38{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
  39{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
  40{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
  41{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},     /* sdmmc2_clk */
  42{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
  43{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},         /* sdmmc1_clk */
  44{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
  45{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
  46{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
  47{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
  48{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
  49{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
  50{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
  51{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
  52{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
  53{I2C1_SCL, (PTU | IEN | M0)},                           /* i2c1_scl */
  54{I2C1_SDA, (PTU | IEN | M0)},                           /* i2c1_sda */
  55{I2C2_SCL, (PTU | IEN | M0)},                           /* i2c2_scl */
  56{I2C2_SDA, (PTU | IEN | M0)},                           /* i2c2_sda */
  57{I2C3_SCL, (PTU | IEN | M0)},                           /* i2c3_scl */
  58{I2C3_SDA, (PTU | IEN | M0)},                           /* i2c3_sda */
  59{I2C4_SCL, (PTU | IEN | M0)},                           /* i2c4_scl */
  60{I2C4_SDA, (PTU | IEN | M0)},                           /* i2c4_sda */
  61{UART3_CTS_RCTX, (PTU | IEN | M0)},                     /* uart3_tx */
  62{UART3_RTS_SD, (M0)},                                   /* uart3_rts_sd */
  63{UART3_RX_IRRX, (IEN | M0)},                            /* uart3_rx */
  64{UART3_TX_IRTX, (M0)}                                   /* uart3_tx */
  65
  66};
  67
  68const struct pad_conf_entry wkup_padconf_array_essential[] = {
  69
  70{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
  71{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
  72{PAD1_SYS_32K, (IEN | M0)}       /* sys_32k */
  73
  74};
  75
  76#endif  /* _OMAP4_MUX_DATA_H_ */
  77