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24#ifndef __ASM_ARCH_MX31_IMX_REGS_H
25#define __ASM_ARCH_MX31_IMX_REGS_H
26
27#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28#include <asm/types.h>
29
30
31struct clock_control_regs {
32 u32 ccmr;
33 u32 pdr0;
34 u32 pdr1;
35 u32 rcsr;
36 u32 mpctl;
37 u32 upctl;
38 u32 spctl;
39 u32 cosr;
40 u32 cgr0;
41 u32 cgr1;
42 u32 cgr2;
43 u32 wimr0;
44 u32 ldc;
45 u32 dcvr0;
46 u32 dcvr1;
47 u32 dcvr2;
48 u32 dcvr3;
49 u32 ltr0;
50 u32 ltr1;
51 u32 ltr2;
52 u32 ltr3;
53 u32 ltbr0;
54 u32 ltbr1;
55 u32 pmcr0;
56 u32 pmcr1;
57 u32 pdr2;
58};
59
60struct cspi_regs {
61 u32 rxdata;
62 u32 txdata;
63 u32 ctrl;
64 u32 intr;
65 u32 dma;
66 u32 stat;
67 u32 period;
68 u32 test;
69};
70
71
72#define WDOG_ENABLE (1 << 2)
73#define WDOG_WT_SHIFT 8
74struct wdog_regs {
75 u16 wcr;
76 u16 wsr;
77 u16 wrsr;
78};
79
80
81struct iim_regs {
82 u32 iim_stat;
83 u32 iim_statm;
84 u32 iim_err;
85 u32 iim_emask;
86 u32 iim_fctl;
87 u32 iim_ua;
88 u32 iim_la;
89 u32 iim_sdat;
90 u32 iim_prev;
91 u32 iim_srev;
92 u32 iim_prog_p;
93 u32 iim_scs0;
94 u32 iim_scs1;
95 u32 iim_scs2;
96 u32 iim_scs3;
97};
98
99struct mx3_cpu_type {
100 u8 srev;
101 u32 v;
102};
103
104#define IOMUX_PADNUM_MASK 0x1ff
105#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
106
107
108
109
110enum iomux_pad_config {
111 PAD_CTL_NOLOOPBACK = 0x0 << 9,
112 PAD_CTL_LOOPBACK = 0x1 << 9,
113 PAD_CTL_PKE_NONE = 0x0 << 8,
114 PAD_CTL_PKE_ENABLE = 0x1 << 8,
115 PAD_CTL_PUE_KEEPER = 0x0 << 7,
116 PAD_CTL_PUE_PUD = 0x1 << 7,
117 PAD_CTL_100K_PD = 0x0 << 5,
118 PAD_CTL_100K_PU = 0x1 << 5,
119 PAD_CTL_47K_PU = 0x2 << 5,
120 PAD_CTL_22K_PU = 0x3 << 5,
121 PAD_CTL_HYS_CMOS = 0x0 << 4,
122 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
123 PAD_CTL_ODE_CMOS = 0x0 << 3,
124 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
125 PAD_CTL_DRV_NORMAL = 0x0 << 1,
126 PAD_CTL_DRV_HIGH = 0x1 << 1,
127 PAD_CTL_DRV_MAX = 0x2 << 1,
128 PAD_CTL_SRE_SLOW = 0x0 << 0,
129 PAD_CTL_SRE_FAST = 0x1 << 0
130};
131
132
133
134
135
136
137
138enum iomux_pins {
139 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
140 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
141 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
142 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
143 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
144 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
145 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
146 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
147 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
148 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
149 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
150 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
151 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
152 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
153 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
154 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
155 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
156 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
157 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
158 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
159 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
160 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
161 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
162 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
163 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
164 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
165 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
166 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
167 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
168 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
169 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
170 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
171 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
172 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
173 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
174 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
175 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
176 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
177 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
178 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
179 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
180 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
181 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
182 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
183 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
184 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
185 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
186 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
187 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
188 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
189 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
190 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
191 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
192 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
193 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
194 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
195 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
196 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
197 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
198 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
199 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
200 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
201 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
202 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
203 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
204 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
205 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
206 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
207 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
208 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
209 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
210 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
211 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
212 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
213 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
214 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
215 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
216 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
217 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
218 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
219 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
220 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
221 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
222 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
223 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
224 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
225 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
226 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
227 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
228 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
229 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
230 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
231 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
232 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
233 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
234 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
235 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
236 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
237 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
238 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
239 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
240 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
241 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
242 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
243 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
244 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
245 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
246 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
247 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
248 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
249 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
250 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
251 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
252 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
253 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
254 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
255 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
256 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
257 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
258 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
259 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
260 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
261 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
262 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
263 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
264 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
265 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
266 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
267 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
268 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
269 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
270 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
271 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
272 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
273 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
274 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
275 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
276 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
277 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
278 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
279 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
280 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
281 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
282 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
283 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
284 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
285 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
286 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
287 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
288 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
289 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
290 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
291 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
292 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
293 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
294 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
295 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
296 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
297 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
298 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
299 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
300 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
301 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
302 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
303 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
304 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
305 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
306 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
307 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
308 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
309 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
310 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
311 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
312 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
313 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
314 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
315 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
316 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
317 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
318 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
319 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
320 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
321 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
322 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
323 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
324 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
325 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
326 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
327 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
328 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
329 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
330 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
331 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
332 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
333 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
334 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
335 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
336 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
337 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
338 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
339 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
340 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
341 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
342 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
343 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
344 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
345 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
346 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
347 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
348 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
349 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
350 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
351 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
352 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
353 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
354 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
355 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
356 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
357 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
358 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
359 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
360 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
361 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
362 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
363 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
364 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
365 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
366 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
367 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
368 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
369 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
370 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
371 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
372 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
373 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
374 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
375 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
376 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
377 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
378 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
379 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
380 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
381 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
382 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
383 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
384 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
385 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
386 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
387 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
388 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
389 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
390 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
391 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
392 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
393 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
394 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
395 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
396 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
397 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
398 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
399 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
400 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
401 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
402 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
403 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
404 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
405 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
406 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
407 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
408 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
409 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
410 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
411 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
412 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
413 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
414 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
415 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
416 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
417 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
418 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
419 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
420 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
421 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
422 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
423 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
424 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
425 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
426 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
427 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
428 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
429 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
430 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
431 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
432 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
433 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
434 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
435 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
436 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
437 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
438 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
439 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
440 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
441 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
442 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
443 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
444 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
445 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
446 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
447 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
448 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
449 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
450 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
451 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
452 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
453 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
454 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
455 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
456 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
457 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
458 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
459 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
460 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
461 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
462 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
463 MX31_PIN_PWMO = IOMUX_PIN(9, 324),
464 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
465 MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
466 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
467};
468
469
470#define CCM_RCSR_NF16B (1 << 31)
471#define CCM_RCSR_NFMS (1 << 30)
472
473#endif
474
475#define __REG(x) (*((volatile u32 *)(x)))
476#define __REG16(x) (*((volatile u16 *)(x)))
477#define __REG8(x) (*((volatile u8 *)(x)))
478
479#define CCM_BASE 0x53f80000
480#define CCM_CCMR (CCM_BASE + 0x00)
481#define CCM_PDR0 (CCM_BASE + 0x04)
482#define CCM_PDR1 (CCM_BASE + 0x08)
483#define CCM_RCSR (CCM_BASE + 0x0c)
484#define CCM_MPCTL (CCM_BASE + 0x10)
485#define CCM_UPCTL (CCM_BASE + 0x14)
486#define CCM_SPCTL (CCM_BASE + 0x18)
487#define CCM_COSR (CCM_BASE + 0x1C)
488#define CCM_CGR0 (CCM_BASE + 0x20)
489#define CCM_CGR1 (CCM_BASE + 0x24)
490#define CCM_CGR2 (CCM_BASE + 0x28)
491
492#define CCMR_MDS (1 << 7)
493#define CCMR_SBYCS (1 << 4)
494#define CCMR_MPE (1 << 3)
495#define CCMR_PRCS_MASK (3 << 1)
496#define CCMR_FPM (1 << 1)
497#define CCMR_CKIH (2 << 1)
498
499#define MX31_IIM_BASE_ADDR 0x5001C000
500
501#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
502#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
503#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
504#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
505#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
506#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
507#define PDR0_MCU_PODF(x) ((x) & 0x7)
508
509#define PLL_PD(x) (((x) & 0xf) << 26)
510#define PLL_MFD(x) (((x) & 0x3ff) << 16)
511#define PLL_MFI(x) (((x) & 0xf) << 10)
512#define PLL_MFN(x) (((x) & 0x3ff) << 0)
513
514#define WEIM_ESDCTL0 0xB8001000
515#define WEIM_ESDCFG0 0xB8001004
516#define WEIM_ESDCTL1 0xB8001008
517#define WEIM_ESDCFG1 0xB800100C
518#define WEIM_ESDMISC 0xB8001010
519
520#define ESDCTL_SDE (1 << 31)
521#define ESDCTL_CMD_RW (0 << 28)
522#define ESDCTL_CMD_PRECHARGE (1 << 28)
523#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
524#define ESDCTL_CMD_LOADMODEREG (3 << 28)
525#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
526#define ESDCTL_ROW_13 (2 << 24)
527#define ESDCTL_ROW(x) ((x) << 24)
528#define ESDCTL_COL_9 (1 << 20)
529#define ESDCTL_COL(x) ((x) << 20)
530#define ESDCTL_DSIZ(x) ((x) << 16)
531#define ESDCTL_SREFR(x) ((x) << 13)
532#define ESDCTL_PWDT(x) ((x) << 10)
533#define ESDCTL_FP(x) ((x) << 8)
534#define ESDCTL_BL(x) ((x) << 7)
535#define ESDCTL_PRCT(x) ((x) << 0)
536
537#define WEIM_BASE 0xb8002000
538#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
539#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
540#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
541
542#define IOMUXC_BASE 0x43FAC000
543#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
544#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
545#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
546
547#define IPU_BASE 0x53fc0000
548#define IPU_CONF IPU_BASE
549
550#define IPU_CONF_PXL_ENDIAN (1<<8)
551#define IPU_CONF_DU_EN (1<<7)
552#define IPU_CONF_DI_EN (1<<6)
553#define IPU_CONF_ADC_EN (1<<5)
554#define IPU_CONF_SDC_EN (1<<4)
555#define IPU_CONF_PF_EN (1<<3)
556#define IPU_CONF_ROT_EN (1<<2)
557#define IPU_CONF_IC_EN (1<<1)
558#define IPU_CONF_SCI_EN (1<<0)
559
560#define ARM_PPMRR 0x40000015
561
562#define WDOG_BASE 0x53FDC000
563
564
565
566
567#define GPIO1_BASE_ADDR 0x53FCC000
568#define GPIO2_BASE_ADDR 0x53FD0000
569#define GPIO3_BASE_ADDR 0x53FA4000
570#define GPIO_DR 0x00000000
571#define GPIO_GDIR 0x00000004
572#define GPIO_PSR 0x00000008
573
574
575
576
577
578
579#define MUX_CTL_OUT_GPIO_DR (0 << 4)
580#define MUX_CTL_OUT_FUNC (1 << 4)
581#define MUX_CTL_OUT_ALT1 (2 << 4)
582#define MUX_CTL_OUT_ALT2 (3 << 4)
583#define MUX_CTL_OUT_ALT3 (4 << 4)
584#define MUX_CTL_OUT_ALT4 (5 << 4)
585#define MUX_CTL_OUT_ALT5 (6 << 4)
586#define MUX_CTL_OUT_ALT6 (7 << 4)
587#define MUX_CTL_IN_NONE (0 << 0)
588#define MUX_CTL_IN_GPIO (1 << 0)
589#define MUX_CTL_IN_FUNC (2 << 0)
590#define MUX_CTL_IN_ALT1 (4 << 0)
591#define MUX_CTL_IN_ALT2 (8 << 0)
592
593#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
594#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
595#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
596#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
597
598
599
600#define MUX_CTL_USBH2_DATA1 0x40
601#define MUX_CTL_USBH2_DIR 0x44
602#define MUX_CTL_USBH2_STP 0x45
603#define MUX_CTL_USBH2_NXT 0x46
604#define MUX_CTL_USBH2_DATA0 0x47
605#define MUX_CTL_USBH2_CLK 0x4B
606#define MUX_CTL_RTS1 0x7c
607#define MUX_CTL_CTS1 0x7d
608#define MUX_CTL_DTR_DCE1 0x7e
609#define MUX_CTL_DSR_DCE1 0x7f
610#define MUX_CTL_CSPI2_SCLK 0x80
611#define MUX_CTL_CSPI2_SPI_RDY 0x81
612#define MUX_CTL_RXD1 0x82
613#define MUX_CTL_TXD1 0x83
614#define MUX_CTL_CSPI2_MISO 0x84
615#define MUX_CTL_CSPI2_SS0 0x85
616#define MUX_CTL_CSPI2_SS1 0x86
617#define MUX_CTL_CSPI2_SS2 0x87
618#define MUX_CTL_CSPI1_SS2 0x88
619#define MUX_CTL_CSPI1_SCLK 0x89
620#define MUX_CTL_CSPI1_SPI_RDY 0x8a
621#define MUX_CTL_CSPI2_MOSI 0x8b
622#define MUX_CTL_CSPI1_MOSI 0x8c
623#define MUX_CTL_CSPI1_MISO 0x8d
624#define MUX_CTL_CSPI1_SS0 0x8e
625#define MUX_CTL_CSPI1_SS1 0x8f
626#define MUX_CTL_STXD6 0x90
627#define MUX_CTL_SRXD6 0x91
628#define MUX_CTL_SCK6 0x92
629#define MUX_CTL_SFS6 0x93
630
631#define MUX_CTL_STXD3 0x9C
632#define MUX_CTL_SRXD3 0x9D
633#define MUX_CTL_SCK3 0x9E
634#define MUX_CTL_SFS3 0x9F
635
636#define MUX_CTL_NFC_WP 0xD0
637#define MUX_CTL_NFC_CE 0xD1
638#define MUX_CTL_NFC_RB 0xD2
639#define MUX_CTL_NFC_WE 0xD4
640#define MUX_CTL_NFC_RE 0xD5
641#define MUX_CTL_NFC_ALE 0xD6
642#define MUX_CTL_NFC_CLE 0xD7
643
644
645#define MUX_CTL_CAPTURE 0x150
646#define MUX_CTL_COMPARE 0x151
647
648
649
650
651#define IOMUX_MODE_POS 9
652#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
653
654
655
656
657
658#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
659#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
660#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
661#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
662
663#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
664#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
665#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
666#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
667#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
668#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
669 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
670#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
671
672#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
673#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
674#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
675#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
676#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
677#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
678 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
679#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
680
681#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
682#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
683
684
685#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
686#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
687#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
688#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
689#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
690#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
691#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
692#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
693#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
694#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
695#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
696#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
697#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
698#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
699#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
700#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
701#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
702#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
703#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
704#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
705#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
706#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
707#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
708#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
709#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
710#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
711#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
712#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
713#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
714
715
716
717
718#define IPU_MEM_BASE 0x70000000
719#define CSD0_BASE 0x80000000
720#define CSD1_BASE 0x90000000
721#define CS0_BASE 0xA0000000
722#define CS1_BASE 0xA8000000
723#define CS2_BASE 0xB0000000
724#define CS3_BASE 0xB2000000
725#define CS4_BASE 0xB4000000
726#define CS4_PSRAM_BASE 0xB5000000
727#define CS5_BASE 0xB6000000
728#define PCMCIA_MEM_BASE 0xC0000000
729
730
731
732
733#define NFC_BASE_ADDR 0xB8000000
734
735
736
737
738#define IRAM_BASE_ADDR 0x1FFFC000
739#define IRAM_SIZE (16 * 1024)
740
741#define MX31_AIPS1_BASE_ADDR 0x43f00000
742#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
743
744
745
746#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
747#define MXC_EHCI_FORCE_FS (1 << 24)
748#define MXC_EHCI_UTMI_8BIT (0 << 28)
749#define MXC_EHCI_UTMI_16BIT (1 << 28)
750#define MXC_EHCI_SERIAL (1 << 29)
751#define MXC_EHCI_MODE_UTMI (0 << 30)
752#define MXC_EHCI_MODE_PHILIPS (1 << 30)
753#define MXC_EHCI_MODE_ULPI (2 << 30)
754#define MXC_EHCI_MODE_SERIAL (3 << 30)
755
756
757#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
758#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
759#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
760#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
761#define MXC_EHCI_INTERFACE_MASK (0xf)
762
763#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
764#define MXC_EHCI_TTL_ENABLED (1 << 6)
765
766#define MXC_EHCI_INTERNAL_PHY (1 << 7)
767#define MXC_EHCI_IPPUE_DOWN (1 << 8)
768#define MXC_EHCI_IPPUE_UP (1 << 9)
769
770#endif
771
